Dr. Oniga István

1. LOGIKAI TERVEZÉS HARDVERLEÍRÓ NYELVEN Dr. Oniga István

2. Memory • In this chapter we will show how to implement memory on the Nexys-2 board by • using the following six examples: • Example 27 - A Verilog ROM • Example 28 - Distributed RAM/ROM • Example 29 - A Stack • Example 30 - Block RAM • Example 31 - External RAM • Example 32 - External Flash Memory • Example 27 will show how to implement a small read-only memory (ROM) using Verilog. • For larger memories you can use the Core Generator to implement either distributed RAM (or ROM) that uses the FPGA LUTs (Example 28) or Block RAM that uses the block RAM within the FPGA (Example 30). • For even larger memories you can access the 16 Mbytes of external RAM (Example 31) or 16 Mbytes of external flash memory (Example 32), which are on the Nexys-2 board. • Example 29 shows how to use distributed RAM to implement a stack.

3. A Verilog ROM • 3-bit address bus, addr[2:0], 8-bit data bus M[7:0] • For example contents of the ROM at the address • addr[2:0] = 3'b1 10 is 'h6C To implement this ROM in Verilog it is convenient to store the eight bytes as a single 64-bit hex constant as shown below reg [N-l: O] rom [O:N_WORDS-l]; N is the number of bits per ROM word = 8 The parameter N _ WORDS is the number of N-bit words in the ROM = 8 parameter data = ' h00C8F9AF64956CD4;

4. A Verilog ROM • module rom8 ( • input wire [2:0] addr , • output wire [7:0] M • ) ; • parameter N = 8; // no. of bits in rom word • parameter N_WORDS = 8 ; //no. of words in rom • reg [N-1:0] rom [0:N_WORDS-l]; • parameter data = 'h00C8F9AF64956CD4; • parameter IXLEFT = N*N_WORDS - 1; // left index of data • integer i; • initial • begin • for(i=0; i<N_WORDS; i=i+l) • rom[i] = data[(IXLEFT-N*i)-:N]; • end • assign M = rom[addr]; • endmodule • Part-selector operator: • “ - : “ separates the starting bit IXLEFT-N*I from the width (N) counting down • “ + : “ would define a width counting up • For i=1 => rom[1] = data[(63-8)-:8 = data[55-:8] = data[55:48] wich selects the byte C8

5. A Verilog ROM simulation

6. Distributed RAM/ROM Core Generator:

7. Distributed RAM/ROM Core Generator:

8. Distributed RAM/ROM The content of the ROM can be defined using a .coe file with the format: ; Example 28 Initialization file for a 16x8 distributed ROM memory_initialization_radix = 16; memory_initialization_vector = 0 C8 F9 AF 64 95 6C D4 39 E7 5A 96 84 37 28 4C;

9. Distributed RAM/ROM The component dist_rom16 will be created and all files will be generated.

10. Distributed RAM/ROM simulation