Concepts of System Design

1. Concepts of System Design • The example used here is a Bit-pattern associative router. It has components that include: • Input and Output Ports • Routing and Arbitration module • The Switch as well as local node circuitry • The idea is to understand what the system requirements are and what each component’s fuction is. • In this case we design just the routing and arbitration unit • Its function is to get the message header and determine the appropriate route the message must follow to reach its destination.

2. Router Architecture local node input ports outputports switch routing & arbitration

3. Associative router scheme output port destination address priority routing function port assignment Selection function

4. General routing function destination address

5. Routing function IF cond THEN assign(out_put) Cond =

6. Case statement IF cond1 THEN assign(out_port1) ELSE IF cond2 THEN assign(out_port2) ELSE IF cond3 THEN assign(out_port3) . . . ELSE IF condN THEN assign(out_portN)

7. Router organization Normal operation destination address to switching network Search argument register Port assignment Register Bit-Pattern selection function (SF) row select row select (DCAM) Refresh (DCAM) no match Refresh (DRAM) (from input port) (output port) Port Associative Assignment Unit (DRAM) The Blue Rows indicate matching words/addresses and Only one is selected and routed

8. Programming mode Program Data Program Data (Current Address) (Output Port Assignment) Search argument register Input Latch Input Latch Port assignment Register Bit-Pattern selection function (SF) row select row select (DCAM) Refresh (DCAM) no match Refresh (DRAM) The row select, selects a word to write to and the action is the same for both the Dynamic Content Addressable Memory (CAM) and the Dynamic RAM (DRAM)

9. Basic element of the bit-pattern associative unit One of many flavors Of dynamic CAM Bit Bit write sb1 sb0 read Match line Evaluate

10. Tenary digit stored in the DCAM cell

11. Basic cell of the selection function w/o priority lookahead

12. 4-bit encoder w/o lookahead

13. Basic cell of the selection function with priority lookahead

14. 4-bit priority lookahead encoder

15. The Refresh Basic Cell Bit Bit • DCAM Refresh • Good For DRAM too read read VDD VDD write write C2MOS Refresh Register

16. F1 Two phase clocking T21 F2 T12 Get input 1 Latch & pass input 1 to bit lines Get input 2 Latch & pass input 2 to bit lines Get input 3 Get input 4 Latch & pass input 2 to bit lines Input Latch operation Compare 1 input to stored data. Evaluate matchline @ T21 & F2 Write data back after refreshing (@ T21 & F1 Compare 2 input to stored data. Evaluate matchline @ T21 & F2 Compare 3 input to stored data. Evaluate matchline @ T21 & F2 Write data back after refreshing (@ T21 & F1 Read & refresh data Precharge bitlines Read & refresh data Matching Unit (DCAM) operation (timing events) Reset priority encoder DRAM Select ignored Precharge priority line Reset priority encoder Precharge priority line Reset priority encoder Precharge priority line Reset priority encoder Select DRAM Get Match Get Match Select DRAM Get Match Priority Encoder operation (timing events) Precharge DRAM bitlines Read data 1 from selected row, latch data. @ F2 send data out Precharge DRAM bitlines Read data 2 from selected row, latch data. @ F2 send data out Precharge DRAM bitlines Precharge DRAM bitlines Output port activity Timing Operation • Match Operation Timing Sequence