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Enhancing Performance via Pipelining: ASMs as an Alternative SM Design Tool

This lecture covers the concept of enhancing performance through pipelining and explores Algorithmic State Machines (ASMs) as an alternative design tool. It discusses the use of ASMs in computer architecture, including topics such as registers, data paths, and clock rates.

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Enhancing Performance via Pipelining: ASMs as an Alternative SM Design Tool

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  1. Computer Architecture: IntroLecture 7- Enhancing performance via pipelining; ASMs as an alternative SM design tool J. Schmalzel S. Mandayam

  2. Dbus RW Register File DA AA Const MB MuxB Aout Dout FS Function Unit Status Din MD MuxD Simple Model Data Path (7-18) n-bit bus Signal BA Dbus

  3. Maximum Clock Rate Consider delays through each functional element—e.g., Register File: 1.4 ns Mux’s: 0.6 ns Function Unit: 2.0 ns Fmax = 1/Ttotal where Ttotal =  Ti For the above example, Fmax = 1/4.0 = 250 MHz

  4. Considerations for Ti • Combinatorial delays • Propagation delay (numbers of gate levels) • Rise times and fall times • Sequential delays • Propagation delay • Setup and hold times (w.r.t. clock edge)

  5. How to Speed Up Architecture? • Brute force: • Technology speed up (scaling, power) • Parallelism • Architecture alternatives: • Pipelining

  6. Pipeline Register Pipeline Register Pipeline Register DP Element 3 DP Element 2 DP Element 1 Pipeline Registers Insert pipeline register between each significant architectural element Speedup is due to sequential clocking through each stage of the pipeline: Fmax= 1/(Tmax + TPR) If we use the same time delays from before, and assume TPR = 0.6 ns, Fmax= 1/(2.0 + 0.6) = 385 MHz

  7. 4-Stage Pipeline Diagram Clock # Opn # Pipeline fills: CK1-CK3; Pipeline is full: CK4-CK5; Pipeline is emptying: CK6-CK8

  8. Description of Pipeline Diagram • Each stage of the pipeline is denoted as A, B, C, D… • Each operation presented to the pipeline is numbered—e.g., 1, 2, 3… • Each clock is numbered: CK1, CK2… • Flush operation is indicated by “—” which suggests nothing is presented to start of pipeline. In actuality, some other operation sequence would be started, but what is shown emphasizes the fact that it takes 3 additional clock cycles to finish what was started.

  9. Pipeline Issues • Delays due to pipeline filling: No useful output for an N-stage pipeline until N clocks • Highest performance when pipeline is full • Periodic need to flush (empty) the pipeline to accommodate branching, etc.

  10. Algorithmic State Machines (ASMs) • State blocks for Moore (1-hot) machines include a State box and Decision box(es). • State boxes correspond to state bubbles on a SD. • Output list is provided in state box • Outputs of input decision box exit the state block and enter other state boxes. Decision boxes correspond to the input test shown on SD arcs into and out of SD bubbles.

  11. Direct Implementation of 1-hot ASMs • State boxes map to D-F/F’s • State block entries map to OR gates • Decision boxes map to AND gates

  12. Control Path • Hard-wired control • Sequencer • Microprogramming (also may see “Microsequencer”)

  13. Questions, Comments, Discussion

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