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#### Youssef Ahmed

my code is this:

"library ieee;

use ieee.std_logic_1164.all;

package andpackage is

component and2 is

port (a, b: IN std_logic;

c: OUT std_logic);

end component and2;

end package andpackage;

entity circuit2 is

port (a, b, x, y: IN std_logic;

d: OUT std_logic);

end entity circuit2;

architecture mixed of circuit2 is

for gate: and2 use entity work.and2(and2);

signal c,z: std_logic;

begin

gate: and2 port map (a,b,c);

d <= c XOR z;

op: process (x,y) is

begin

z <= x OR y;

end process op;

end architecture mixed;"

i get 3 errors, 2 of them say "(vcom-1136) Unknown identifier "std_logic"." while the 3rd just says "VHDL Compiler exiting", any help would be greatly appreciated, thanks in advance.