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Cyclic Prefix Insertion for OFDM Systems. Xiaofei Dong. Buffer. Cyclic Prefix Insertion. sink_ready. Cyclic Prefix Size. dout_valid. CP Size. dout_sop. dout_eop. Cyclic Prefix Insertion. din_ready. dout_real. dout_imag. din_valid. FFT Size. FFT Size. din_sop. din_eop.
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Cyclic Prefix Insertion for OFDM Systems Xiaofei Dong
Buffer Cyclic Prefix Insertion sink_ready Cyclic Prefix Size dout_valid CP Size dout_sop dout_eop Cyclic Prefix Insertion din_ready dout_real dout_imag din_valid FFT Size FFT Size din_sop din_eop Cyclic Prefix Size din_real IFFT v7.1 Variable Streaming din_imag Write Read dout_ready SRAM FFT Size SRAM clk_slow clk_fast
Cyclic Prefix Insertion Features • FFT size can be changed at run time on a packet basis • Cyclic prefix size can be changed at run time on a packet basis • Cyclic prefix size can have arbitrary value • FFT MegaCore input is in natural order, and output is in bit reversed order • Bit reversal and cyclic prefix insertion are done at the same time using two packet-size memory buffers • Data width, memory depth, FFT packet size width, cyclic prefix port width can be parameterized
Cyclic Prefix Insertion Features - Interface • Input data format • Signed Fixed Point, configurable bit width, default at 16 • Real (din_real) and Imaginary input (din_imag) • Output data format • Signed fixed point, configurable bit width, default at 32 • Real (dout_real) and Imaginary output (dout_imag) • FFT output is not truncated; truncation is done outside of FFT module to reduce memory usage • Input Interfaces: Avalon Streaming • ready signal latency = 0 cycle • Supports back pressue • Output Interface: Avalon Streaming • ready_latency = 4 cylces • supports back pressure
Cyclic Prefix Insertion Features - Clocks • Clk_slow can operate at transmission bandwidth • in this case output data from module is continuous if FFT Size does not change • clk_slow can equal or exceed clk_fast • Clk_fast operates at integer multiple of Clk_slow • higher clk_fast allows more time-sharing to be exploited in IFFT Megacore to minimise resources • Clk_slow and Clk_fast can be asynchronous
Resources: Max FFT Size = 2048 *Fast Clock Fmax is FFT – limited. *Timing for SIII and CIII is preliminary.
Running Simulation • Top level design is \source\ofdm_kernel_Tx.vhd • Simulation TCL Scripts • Run \scripts\ofdm_kernel_msim.tcl • Cyclic Prefix is checked using a Matlab script \sim\outputcheck_c.m • The script compares IFFT output data with ofdm_kernel_Tx output, to check if CP is of correct size and from the last L symbols of current IFFT packet. • The C simulation model for the FFT core is used to generate IFFT output, i.e. input to the cyclic prefix insertion module. • To run the Matlab script, run \sim\outputcheck_c.m from Matlab command line. • Cyclic Prefix size and FFT size can be changed in the test bench \tb\ofdm_kernel_Tx_tb.vhd