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Final Exam (Exam 3) Information

Final Exam (Exam 3) Information. Tues., May 17 th 1 – 2:50 exam written for ~ 1.5 hr length 15% of final grade Mostly short answer Short Verilog examples State Diagrams etc. Open book/notes Calculator is ok. Logistics. Finite State Machines diagrams encoding/design process

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Final Exam (Exam 3) Information

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  1. Final Exam (Exam 3) Information

  2. Tues., May 17th 1 – 2:50 exam written for ~ 1.5 hr length 15% of final grade Mostly short answer Short Verilog examples State Diagrams etc. Open book/notes Calculator is ok Logistics

  3. Finite State Machines diagrams encoding/design process flip-flop level design Moore vs. Mealy Verilog for FSM naming states separation of combinational and sequential blocks State Machine Minimization process for detecting redundancy in FSMs Coverage • Clocking • Clock skew and distribution • setup and hold time constraints • Synchronization • Avoiding metastability • (synchronizers) • Debouncing inputs • Controlling pulse widths • Memories • Basics of: • SRAM • DRAM • Compare/contrast • Implementation • FPGAs/CPLDs

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