Create Presentation
Download Presentation

Download Presentation

On the Need for Statistical Timing Analysis

Download Presentation
## On the Need for Statistical Timing Analysis

- - - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - - -

**On the Need for Statistical Timing Analysis**Farid N. Najm University of Toronto f.najm@utoronto.ca**Introduction**• Increased process variability leads to chip timing variability and lower timing yield • Traditionally, corner-analysis (worst-case files) has been used to manage timing variability • Corner analysis has some disadvantages • Statistical Static Timing Analysis (SSTA) has been proposed as an alternative approach • SSTA has its own disadvantages • Perhaps an alternative “best of both worlds” approach is required: • Use statistical analysis to better choose the corners or the margins to be used in a traditional STA approach**Generation of Corner-Case Files**• Principal Components Analysis de-correlates SPICE parameters and captures bulk of variations • Process parameter corners chosen to maximize MOSFET performance yield**Disadvantages of Corner Analysis**• Some disadvantages: • Corners should maximize circuit yield, not device yield • Goal is to bracket most (say, 99.73%) of what? • individual process variable space? • typical transistor strength? • typical gate/cell delay? • overall circuit performance? • Ideally, one would like #4, but traditionally go with #2 • There are too many corners • Cannot take care of within-die variations • Corner analysis is overkill • One is capturing much more yield (performance spread) than one really needs to • Cannot determine how robust the design is**Too Many Corners**• With more process parameters, the number of process corners increases exponentially • However, there have been recent proposals to reduce the number of corners to be considered • Corner clustering (Sengupta et al., ISQED-04) • This method also allows one to choose corners so as to bracket circuit performance, instead of device performance • Quadratic circuit response, RSM: g(X) = a + bX + XTBX • Solution: X vector that minimizes and maximizes g(X) • Cluster corners that are close in the parameter space**Case Files & Intra-Die Variations**• Traditional corner analysis cannot take care of within-die variations • Heuristic techniques are used within some traditional STA tools to approximately take care of within-die effects • The crux of the problem lies in the systematic within-die variations • Random within-die variations “cancel out” on a path • They don’t exactly cancel out, but their net result is reduced • The overall impact of within-die variations on circuit delay arguably remains small compared to die-to-die variations (S. Samaan, ICCAD-04)**Too Much Guardbanding**• Corner analysis becomes “overkill” when the implicit yield target becomes too large • Not always the case in corner analysis! • Assume that a nominal value of yield is what covers the ± 3 of a standard normal distribution: Y0= 99.73% • Whether corner analysis is overkill or not depends on the performance metric • If g(X) = Xi (i = 1 ,…, n), then Y (3n1/2) - (-3n1/2) > Y0 • Setting Xi at ± 3 is overkill • If g(X) = max (Xi) then Y n(3) - n(-3) < Y0 • Setting Xi at ± 3 is NOT overkill • It also depends on the shape of the acceptability region**Assessment**• The straightforward nature of corner-case analysis has made it the method of choice in industry • It has some limitations: • Need to determine corners based on circuit performance • Location of corners depends on acceptability region • Need to reduce the number of corners to be covered • Cannot determine how robust the design is • Nevertheless, criticisms do not dismiss this approach altogether**Statistical Timing Analysis**• Recently, “Statistical Static Timing Analysis” (SSTA) has been proposed • Deal with circuit timing uncertainty • An alternative to corner analysis • Basic Idea: • Propagate delay distributions, instead of deterministic delays, in the timing graph • Compute node and path delay distributions • Estimate the distribution of circuit delay as the joint distribution of path delays • Find the chip timing yield from circuit delay distribution**Statistical Timing Analysis**• How to handle different types of delay correlations ? • Within-die systematic correlation • Path sharing (reconvergent fanout) • Dependence on global sources of variations • How to propagate distributions in the timing graph ? • The statistical MAX function • Statistical SUM function • What types of distributions to use ? • Gaussian, or arbitrary distributions ? • Distinct trends: • Block-based statistical timing • Path-based statistical timing**Block-Based SSTA**• Propagate distributions of arrival times in the timing graph of the block to get circuit delay distribution • Path distributions are available only indirectly**The MAX Operation**• Arrival times are “MAX-ed” at the nodes of the graph • Circuit delay distribution is obtained on the primary outputs • The various methods differ in: • How the MAX operation is performed • Assumptions on the nature of the distributions (Gaussian/not) • Whether and how correlation is taken care of**Overview: Block-Based Methods**• A key difference among block-based methods lies in whether delays are assumed Gaussian or arbitrary • Two Gaussian approaches both use decomposition, but differ in what underlying variables are used • Visweswariah et al. derive correlations from global sources of variation • Sapatnekar et al. perform PCA on the spatial correlations • Two non-Gaussian approaches differ in the propagation algorithm of arrival times • Blaauw et al. use conservative bounds on delay distributions • Devgan et al. use piece-wise linear approximations**Path-Based Methods**• Path delay distributions are expressed as functions of the underlying sources of variation • Gate delay distributions are added to get path delay distribution • Literature by: Nassif, Jess, Orshansky, Bowman • Circuit delay distribution is obtained from the joint probability of path delays • Circuit delay = MAX(all path delays) • Flow: • Enumerate all critical paths • Estimate path delay distributions • Use multi-dimensional integration to combine all paths • Estimate the timing yield**Assessment**• The problem of propagating delay distributions along paths or through blocks is now “solved” • Yet, this does not mean that SSTA is now “solved”! • Key problems in the proposed methods of SSTA • What does one do with all these distributions?! • Unless if the full chip is “timed” flat, require change in methodology: cannot “time” a path or block in isolation • Correlation handling requires layout information, hence cannot be used pre-placement during circuit design/optimization • Not clear how to get correlation statistics from the process; a disconnect between process and EDA**Practical SSTA**• Desirable features of a practical SSTA approach: • Must require minimal statistical process data • Must account for correlated and uncorrelated variations • Must be usable pre-placement to enable design optimization • Must be applicable to “early design” with uncertain circuitry, in order to allow one to time a path/block in isolation • One can envision three types of SSTA: • Process-specific, not design-specific, during early design • Design-specific, not placement-specific, during circuit design • Placement-specific, during physical design • A mix of the three types of SSTA would constitute a practical framework for managing timing variability**An Early Design Approach**• A recent approach (Najm and Menezes, DAC-04) is applicable during early design • Employ notion of generic paths to develop an approach which is process-specific, not design-specific • The ability to handle early (uncertain) design is key to being able to time a path/block in isolation! • Shift focus from the specific design to a design type • What are a typical transistor/gate in this technology? • What is a typical path length in this class of design? • Assume the circuit or block consists of a large number of such “generic paths”**Conclusions**• Process variability is a key factor of timing yield loss and deterioration of circuit performance • Traditional corner analysis has some limitations, but they are not insurmountable • Statistical timing analysis is being proposed as an alternative, but it has its own limitations • Perhaps one can have it both ways • Combine features of statistical analysis and corner-case files • Derive virtual corners and timing margins for a yield-aware timing verification • This continues to be an active research topic