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Requirements of CMS on the BST 

LHC Experiment Accelerator Data Exchange Working Group. Requirements of CMS on the BST . 1. Trigger Fast Control 2. Detector Control System 3. Requirements on BST. J. Varela LIP Lisbon / CERN. Trigger Fast Control. TTCmi. DAQ Event Managers. Global Trigger. LHC-BST GPS. aTTS.

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Requirements of CMS on the BST 

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  1. LHC Experiment Accelerator Data Exchange Working Group Requirements of CMS on the BST  1. Trigger Fast Control 2. Detector Control System 3. Requirements on BST J. Varela LIP Lisbon / CERN

  2. Trigger Fast Control TTCmi DAQ Event Managers Global Trigger LHC-BST GPS aTTS Central Control Partition Control Partition Control Partition Control Local Triggers Local Control Local Control Local Control BST TTC sTTS TTC sTTS TTC sTTS FrontEnd FrontEnd FrontEnd TTCrx TTCrx TTCrx

  3. Trigger Control Components BST link To EVM GLOBAL TRIGGER CRATE To/from aTTS TTCmi Central Trigger Control ClockOrbit TTC (x 32) (x 32) TTS Local Triggers Fast Merging Module BST link CPU int F M M TTCex TTCci F M M LTC TTS ... ... FMM TTC SYNC TTS TTS Link Subdetector Master TTC Crate TTC Link Local Trigger Controller From/To SUBDETECTOR FRONTEND CRATES

  4. TTCci Module • TTCci Functions: • Selecting Central or Local control • Internal storage of B commands • Timing of B commands • Internal Trigger generation • L1A and B-data transmission Interface to TTC optical distribution Replaces TTCvi Development by Tony Rohlev (Wisconsin/CERN)

  5. Trigger Interface to DAQ Trigger Record to EVM: (Included in Event Record) Begin of event 64 bits //Trigg type, Eventnr, BCnr, SourceID.. Trigger number 24 of 32 //Nr of all L1A hex= „00NN NNNN“ DAQ#+ TriggType + BCnr 20 bits of 32 // 4+4+12 bits , hex=„00DT 0BBB“ Subdetector partitions 32 bits // 1= partition is connected, 0= not connected Event Number 24 bits of 32 // hex= „00NN NNNN“ Orbit number 32 bits Technical trigger bits 32 bits Algo bits_0 32 bits Physics trigger algorithm bits 0...31 Algo bits_1 32 bits Physics trigger algorithm bits 32...63 Algo bits_2 32 bits Physics trigger algorithm bits 64...95 Algo bits_3 32 bits Physics trigger algorithm bits 96...127 Algo bits_4 32 bits reserved for optional upgrade Algo bits_5 32 bits reserved for optional upgrade GPS time_0 32 bits // bytes 0-3 GPS time_1 32 bits // bytes 4-7 End of Event 64 bits //Event length, CRC.. (as for DAQ)

  6. Detector Control System GPS Time allows to correlate Event Data with Detector Control Data • Detector subsystems • HV/LV • Fluids and environment • Cooling • Racks/Crates • Temperatures • Infrastructures • Test systems (Laser, LED, alignment camera etc..) • Detector safety (DSS) • Temperature • Gas • Radiation • Experiment supervision • DCS Resources handling • Alarm and loggings • History data base • External systems communication.

  7. Interface to LHC BST LHC Beam Synchronous Timing System (BST) > BST used to synchronize LHC beam instrumentation > Distribution of BST messages (once per orbit) uses TTC > BST message: 32 bytes, of which 8 bytes for GPS Time Usage in CMS: GPS Time added to Event Record: BST/TTC link to Central Trigger Control (1 link) BST/TTC link to Local Trigger Controllers (10 links) GPS Time and LHC Data added to DCS Data: BST/TTC link to central VME receiver (BOBR) (complementary to access to LHC data via DIP)

  8. BST Message Contents time granularity of 1ms Subject to change ? time granularity of 1turn

  9. BST Overview BOBR Clocks Universal time Machine Events (?) Beam Parameters Real-time commands Hardware triggers Bunch & Turn Clocks BST MESSAGE RECEIVER TTCrx Data Bytes 1 TTC Optical Network BST MESSAGE ASSEMBLER TTC Encoder & Optical Transmit. 1 TTCrx CTC 10 TTCrx LTC CMS specific BST items should be located in racks S1 E 8-10 (LHC, BPTX, BPM) Located in Central Trigger and TTC racks (S1 E 2-4)

  10. Summary of Requirements to BST Distribution of BST messages to the experiment Final specification of BST message content and format Specification of BST/TTC message protocol and timing Update of GPS time once per 10 orbits (or better) CMS specific BST items should be located in racks LHC, BPTX or BPM (S1 E 8-10)

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