A Dynamic Programming Approach to Optimal Integrated Code Generation

1. A Dynamic Programming Approach to Optimal Integrated Code Generation Christoph Keßler Andrzej Bednarski Linköping University (Sweden)

2. Outline • Code generation • Our integrated approach • Implementation and results • Current and future work • Conclusion

3. Code Generation IR-level Instruction scheduling IR-level Reg. Alloc IR-level Reg. Alloc IR IR-level Instruction scheduling Instruction selection Instruction selection Instruction selection Instruction selection Target code Target-level Instruction scheduling Target-level Reg. Alloc Target-level Reg. Alloc Target-level Instruction scheduling

4. Related Work • Heuristics • Optimal approaches • ILP • Dynamic programming • Branch-and-bound • Enumeration • Constraint logic programming

5. Integrated Code Generation IR-level Instruction scheduling IR-level Reg. Alloc IR-level Reg. Alloc IR IR-level Instruction scheduling Instruction selection Instruction selection Integrated Code generation Instruction selection Instruction selection Target code Target-level Instruction scheduling Target-level Reg. Alloc Target-level Reg. Alloc Target-level Instruction scheduling

6. Integrated Approach • Christoph Keßler’s previous work • Scheduling by topological sorting • Dynamic programming • Selection DAG • Time profile • Extended selection DAG Basic block scope of code generation

7. z z’ v v u u scheduled(z) scheduled(z’) Topological Sorting

8. {a,b,c} a c b {b,c} {a,c} {a,b} b c a c a b {c,d} {b} {c,d} {a,e} {b} {a,e} h … … … … … … f g d e a b c Selection Tree

9. Selection DAG • Merge multiple instances of same zero indegree set z in one selection node • Selection DAG • Selection DAG is leveled in n+1 levels • Each schedule S corresponds to one path in the selection DAG

10. {a,b,c} a c b {b,c} {a,c} {a,b} a a b c c b {c,d} {b} {a,e} h … … … f g d e a b c Selection DAG

11. Towards Time Optimization • Machine model • Generic superscalar/VLIW architecture • Single/Multiple issue • From IR level to target level • Instruction selection • Register allocation (homogenous) • Imitate instruction dispatcher behaviour

12. time Time Profile • Window of the instructions scheduled last for each unit that may still influence future scheduling decisions t e f - - c d b - - a - - u1 u2 u3

13. time Extended Selection Node • An extended selection node (z, t, P), summarizes all schedules of scheduled(z) that end with the time profile (t, P). • Pruning (formal proof in the paper) t e f - t’ t’ - c d e f - a f - b - - a c d e c d a - - b - - b - - u1 u2 u3 u1 u2 u3 u1 u2 u3

14. Extended Selection DAG Level 0 Level 1 Level 2 ...

15. Solution Space • Group the extended selection nodes in each level according to execution time • Construct solution space in order of increasing time • Postpones the combinatorial explosion

16. Implementation • C++ • LEDA • XML based architecture description language • LCC as C–front-end

17. Results – Random DAGs

18. Results – Random DAGs

19. Results – FIR Filter

20. Results – Matrix Multiplication

21. Results – Jacobi Grid Relax.

22. Current and Future Work • Time-space profile for irregular register sets • Speculative instruction selection • Extensions of architecture description language • Beyond basic block level • Time-space profiles as connector descriptions

23. Conclusion • Goal: fully integrated code generation • Dynamic programming approach • Time profiles to compressthe solution space • Improved order of solution space construction • Feasible for medium sized basic blocks • Potential for extensions • Alternative to ILP • Home page: www.ida.liu.se/~chrke/optimist