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Crosstalk Driven Routing Resource Assignment. Hailong Yao, Qiang Zhou, Xianlong Hong, Yici Cai EDA Lab., Dept. of Computer Science & Technology Tsinghua University, Beijing 100084, China. Outline. Backgrounds Preliminaries Crosstalk Noise Model CDRRA Algorithm Problem Formulation

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Crosstalk driven routing resource assignment

Crosstalk Driven Routing Resource Assignment

Hailong Yao, Qiang Zhou,

Xianlong Hong, Yici Cai

EDA Lab., Dept. of Computer Science & Technology

Tsinghua University, Beijing 100084, China


Outline
Outline

  • Backgrounds

  • Preliminaries

  • Crosstalk Noise Model

  • CDRRA Algorithm

    • Problem Formulation

    • Underlying Graph Model

    • Overview of the Algorithm

    • Example

  • Experimental Results

  • Conclusion


Backgrounds
Backgrounds

  • As VLSI technology advances, crosstalk noise has become critical in determining the performance of the overall chip.

  • The routing problem is divided into two sequential stages: global routing and detailed routing.

  • Most previous works on crosstalk control are performed during detailed routing stage where the estimation of crosstalk can be accurate but the flexibility is restricted. However, the crosstalk control during global routing can not be accurate enough though it has more freedom.

  • With enough flexibility and fairly accurate net routing information, an intermediate stage proves to be an ideal place to solve this problem.

  • Intermediate stage: Track Assignment (TA) and Cross Point Assignment (CPA).


Previous Works:

  • In , TA problem is studied without considering the crosstalk issue.

  • Some works on crosstalk avoidance during the CPA stage have been done in -.

S. H. Batterywala, N. Shenoy, W. Nicholls, and Hai Zhou, “Track Assignment: A Desirable Intermediate Step Between Global Routing and Detailed Routing,” IEEE International Conference on Computer Aided Design, San Jose, CA, 2002.

H.-P. Tseng, L. Scheffer, and C. Sechen, “Timing and crosstalk driven area routing,” in Proc. 35th ACM/IEEE Design Automation Conf., June 1998, pp. 378–381.

C.-C. Chang and J. Cong, “Pseudo pin assignment with crosstalk noise control,” in Proc. Int. Symp. on Physical Design, pp. 41-47, 2000.

 H.L. Yao, Q. Zhou, X.L. Hong and Y.C. Cai, “Cross Point Assignment Algorithm with Crosstalk Constraint,” Proceedings of the 5th International Conference on ASIC, October, 2003, pp. 352-355.


  • Crosstalk-aware TA is study in -.

  • In -, TA is integrated into global routing and in  it is formulated as an ILP problem.

  • We propose a new crosstalk-aware layer/track assignment heuristic algorithm called Crosstalk Driven Routing Resource Assignment (CDRRA).

T. Xue and E.S. Kuh, “Post global routing crosstalk synthesis,” TCAD, pp. 1418-1430, Dec. 1997.

H. Zhou and D.F. Wong, “Global Routing with Crosstalk Constraints,” in Proc. ACM/IEEE Design Automation Conference, June 1998.

R. Kay, and R.A. Rutenbar, “Wire Packing: A Strong Formulation of Crosstalk-aware Chip-level Track/Layer Assignment with an Efficient Integer Programming Solution,” ISPD ’00, 61-68.


Preliminaries

e

GRC

1

GRG

v

v

1

2

Preliminaries

Fig.1 Global Routing Graph(GRG)


Slice

Merge a row of GRCs

Slice

A horizontal slice: A row of GRCs

slice

track

GRC

A row of GRCs


A

C

B

D

E

Decomposition of a global net in the slices

1

2

3

4

5

6

7

8

9

1

GRC

2

3

4

5

6

7

8

9

Decomposition Result: net segment AC, BD and DE

(Note that A, B, C, D and E are the center points of the corresponding GRCs)


Crosstalk model
Crosstalk Model

  • If a switch event on signal net N1 causes signal net N2 to malfunction, then N1 and N2 are regarded to be sensitive to each other, where N1 is called the aggressor and N2 the victim.

  • Sensitivity rate: the ratio of the number of aggressors for Ni to the total number of signal nets.

  • Sensitivity matrix: S = [si,j]N×Nwhere N is the total number of the signal nets and si,j = 1 if Ni and Nj are sensitive to each other, otherwise si,j = 0.

  • The sensitivity matrix is symmetric.


  • Crosstalk noise depends on the coupling capacitances, the driver resistances, the load capacitances and the input waveforms.

  • Only the capacitive crosstalk noise is considered.

  • Avoid adjacent sensitive nets from running in parallel for a long distance.

  • We assume that only adjacent sensitive nets will violate the crosstalk constraint when their overlap length exceeds a predefined constant MAXOL and dis-adjacent nets will never run into trouble with crosstalk violation.


Problem formulation
Problem Formulation driver resistances, the load capacitances and the input waveforms.

  • CDRRA runs in slice-by-slice manner and only the global nets are considered.

  • For each slice Sk, the assignment of net segments to the routing tracks can be formulated as:

    Φ: N×T→C

    N : net segments inside the slice Sk

    T : the routing tracks of Sk

    C : costs which indicates the consumption of the assignment pairs <ni,tj> (1≤i≤|N|, 1≤j≤|T|).

  • The track assignment problem is to find a feasible set Φ’ = {ci,j | ci,j = Φ(<ni,tj>), 1≤i≤|N|, 1≤j≤|T|} for all the elements in N, where the objective

is minimized


  • The cost for assigning net segment driver resistances, the load capacitances and the input waveforms.ni to the routing track tj is mainly composed of the following items:

    • Layer Cost

    • Obstacle Cost

    • Net Length Cost

  • Besides the items mentioned above, the cost matrix also plays a role in preventing the already assigned nets from coupling with the latter ones.

  • After the cost matrix is constructed, we use linear assignment algorithm to find a minimum cost matching solution.


The underlying graph model
The Underlying Graph Model driver resistances, the load capacitances and the input waveforms.

  • Crosstalk Graph (XG)

    • To stores the information of the sensitivity matrix.

    • XG(V, Exg) is an undirected graph.

    • V: the set of all the nets.

    • Exg: the sensitive relationship between the corresponding nets.

    • If there are two nets sensitive to each other, there is an edge in Exg between their corresponding vertexes in V.


  • The Interval Graph ( driver resistances, the load capacitances and the input waveforms.IG)

    • To stores the net segments’ overlap information according to global routing results.

    • IG(Vig, Eig) is undirected and slice-based.

    • Vig: the set of the net segments inside the current slice.

    • Eig: stores the overlap information between each two net segments.

    • Note: IG is a weighted graph and the weights on the edges in Eig are the values of the overlap lengths.


  • Real Crosstalk Graph ( driver resistances, the load capacitances and the input waveforms.RXG)

    • Only adjacent sensitive nets with their overlap length exceeding the constant MAXOL will violate the crosstalk constraint.

    • Stores the real crosstalk risks.

    • RXG is the subgraph of XG and IG.

    • When two net segments are sensitive to each other according to XG and their overlap length exceeds MAXOL according to IG, then there is an edge in Erxg between the corresponding vertices in Vrxg.

    • When such pair of net segments is assigned to adjacent tracks, a crosstalk violation will occur.

    • The max-clique of RXG stores the maximum set of concurrent crosstalk risking net segments. These net segments should not be assigned adjacent to each other to observe the crosstalk constraint.


  • Tracks’ Adjacency Graph ( driver resistances, the load capacitances and the input waveforms.TAG)

    • Stores the adjacency information of the routing tracks in a slice.

    • Undirected and slice-based.

    • Vtag: the set of routing tracks in the current slice.

    • Etag: stores the adjacency information between the routing tracks.

    • The maximum independent set in TAG stores the maximum number of the disadjacent routing tracks, to which real crosstalk risking net segments in RXG should be assigned.


Example

Net a is not in driver resistances, the load capacitances and the input waveforms.

current slice

d

b

a

Set bound 50

e

c

a) XG

10

b

90

d

30

70

20

70

b

80

c

d

30

e

c

e

c) IG

b) Geometric information of the net segments

b

d

e

b

1

2

4

2

c

c

3

d) RXG

1

3

5

4

d

5

f) TAG

e) Assignment results in a slice

Example

MC={ b, c, d }

MIS={1, 3, 5}

Illustration of the Graph Model


Main steps of cdrra
Main Steps of CDRRA driver resistances, the load capacitances and the input waveforms.

(1) Read in the sensitivity rate and construct the crosstalk graph (XG).

(2) For all the horizontal and vertical slices, DO

(3) Construct the Interval Graph (IG).

(4) Construct the Real Crosstalk Graph (RXG).

(5) Construct the tracks’ adjacency graph (TAG).

(6) Construct the cost matrix for the assignments of net segments onto the routing tracks.

(7) Compute the maximum clique in RXG and the maximum independent set in TAG. Calculate the minimum cost assignment solution using the linear assignment algorithm.

(8) Update IG, RXG, TAG and the cost matrix according to the assignment results. If RXG is NULL, then go to (9), else go to (7).

(9) Compute the maximum clique from IG and assign the net segments onto the remaining routing tracks using the same algorithm until all the net segments are assigned or the routing tracks are not available.

(10) END For


Experimental results
Experimental Results driver resistances, the load capacitances and the input waveforms.

  • Implemented in C programming language on SUN Enterprise E450.

  • Sensitivity rate for all the nets: 0.5


Conclusion
Conclusion driver resistances, the load capacitances and the input waveforms.

  • CDRRA algorithm: to address the crosstalk problem between the global routing and detailed routing stage.

  • Basic idea: to calculate the crosstalk risking net segments by the clique heuristic and then assign them to disadjacent tracks by minimum weighted bipartite matching method.

  • The experimental results indicate that the CDRRA algorithm can greatly improve the final routing layout and eliminate most of the crosstalk violations.


Thank You! driver resistances, the load capacitances and the input waveforms.


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