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William Stallings Computer Organization and Architecture 8 th Edition. Chapter 17 Parallel Processing. Multiple Processor Organization. Single instruction, single data stream - SISD Single instruction, multiple data stream - SIMD Multiple instruction, single data stream - MISD

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William Stallings Computer Organization and Architecture 8 th Edition


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    1. William Stallings Computer Organization and Architecture8th Edition Chapter 17 Parallel Processing

    2. Multiple Processor Organization • Single instruction, single data stream - SISD • Single instruction, multiple data stream - SIMD • Multiple instruction, single data stream - MISD • Multiple instruction, multiple data stream- MIMD

    3. Single Instruction, Single Data Stream - SISD • Single processor • Single instruction stream • Data stored in single memory • Uni-processor

    4. Single Instruction, Multiple Data Stream - SIMD • Single machine instruction • Controls simultaneous execution • Number of processing elements • Lockstep basis • Each processing element has associated data memory • Each instruction executed on different set of data by different processors • Vector and array processors

    5. Multiple Instruction, Single Data Stream - MISD • Sequence of data • Transmitted to set of processors • Each processor executes different instruction sequence • Never been implemented

    6. Multiple Instruction, Multiple Data Stream- MIMD • Set of processors • Simultaneously execute different instruction sequences • Different sets of data • SMPs, clusters and NUMA systems

    7. Taxonomy of Parallel Processor Architectures

    8. MIMD - Overview • General purpose processors • Each can process all instructions necessary • Further classified by method of processor communication

    9. Tightly Coupled - SMP • Processors share memory • Communicate via that shared memory • Symmetric Multiprocessor (SMP) • Share single memory or pool • Shared bus to access memory • Memory access time to given area of memory is approximately the same for each processor

    10. Tightly Coupled - NUMA • Nonuniform memory access • Access times to different regions of memory may differ

    11. Loosely Coupled - Clusters • Collection of independent uniprocessors or SMPs • Interconnected to form a cluster • Communication via fixed path or network connections

    12. Parallel Organizations - SISD

    13. Parallel Organizations - SIMD

    14. Parallel Organizations - MIMD Shared Memory

    15. Parallel Organizations - MIMDDistributed Memory

    16. Symmetric Multiprocessors • A stand alone computer with the following characteristics • Two or more similar processors of comparable capacity • Processors share same memory and I/O • Processors are connected by a bus or other internal connection • Memory access time is approximately the same for each processor • All processors share access to I/O • Either through same channels or different channels giving paths to same devices • All processors can perform the same functions (hence symmetric) • System controlled by integrated operating system • providing interaction between processors • Interaction at job, task, file and data element levels

    17. Multiprogramming and Multiprocessing

    18. SMP Advantages • Performance • If some work can be done in parallel • Availability • Since all processors can perform the same functions, failure of a single processor does not halt the system • Incremental growth • User can enhance performance by adding additional processors • Scaling • Vendors can offer range of products based on number of processors

    19. Block Diagram of Tightly Coupled Multiprocessor

    20. Organization Classification • Time shared or common bus • Multiport memory • Central control unit

    21. Time Shared Bus • Simplest form • Structure and interface similar to single processor system • Following features provided • Addressing - distinguish modules on bus • Arbitration - any module can be temporary master • Time sharing - if one module has the bus, others must wait and may have to suspend • Now have multiple processors as well as multiple I/O modules

    22. Symmetric Multiprocessor Organization

    23. Time Share Bus - Advantages • Simplicity • Flexibility • Reliability

    24. Time Share Bus - Disadvantage • Performance limited by bus cycle time • Each processor should have local cache • Reduce number of bus accesses • Leads to problems with cache coherence • Solved in hardware - see later

    25. Operating System Issues • Simultaneous concurrent processes • Scheduling • Synchronization • Memory management • Reliability and fault tolerance

    26. A Mainframe SMPIBM zSeries • Uniprocessor with one main memory card to a high-end system with 48 processors and 8 memory cards • Dual-core processor chip • Each includes two identical central processors (CPs) • CISC superscalar microprocessor • Mostly hardwired, some vertical microcode • 256-kB L1 instruction cache and a 256-kB L1 data cache • L2 cache 32 MB • Clusters of five • Each cluster supports eight processors and access to entire main memory space • System control element (SCE) • Arbitrates system communication • Maintains cache coherence • Main store control (MSC) • Interconnect L2 caches and main memory • Memory card • Each 32 GB, Maximum 8 , total of 256 GB • Interconnect to MSC via synchronous memory interfaces (SMIs) • Memory bus adapter (MBA) • Interface to I/O channels, go directly to L2 cache

    27. IBM z990 Multiprocessor Structure

    28. Cache Coherence and MESI Protocol • Problem - multiple copies of same data in different caches • Can result in an inconsistent view of memory • Write back policy can lead to inconsistency • Write through can also give problems unless caches monitor memory traffic

    29. Software Solutions • Compiler and operating system deal with problem • Overhead transferred to compile time • Design complexity transferred from hardware to software • However, software tends to make conservative decisions • Inefficient cache utilization • Analyze code to determine safe periods for caching shared variables

    30. Hardware Solution • Cache coherence protocols • Dynamic recognition of potential problems • Run time • More efficient use of cache • Transparent to programmer • Directory protocols • Snoopy protocols

    31. Directory Protocols • Collect and maintain information about copies of data in cache • Directory stored in main memory • Requests are checked against directory • Appropriate transfers are performed • Creates central bottleneck • Effective in large scale systems with complex interconnection schemes

    32. Snoopy Protocols • Distribute cache coherence responsibility among cache controllers • Cache recognizes that a line is shared • Updates announced to other caches • Suited to bus based multiprocessor • Increases bus traffic

    33. Write Invalidate • Multiple readers, one writer • When a write is required, all other caches of the line are invalidated • Writing processor then has exclusive (cheap) access until line required by another processor • Used in Pentium II and PowerPC systems • State of every line is marked as modified, exclusive, shared or invalid • MESI

    34. Write Update • Multiple readers and writers • Updated word is distributed to all other processors • Some systems use an adaptive mixture of both solutions

    35. MESI State Transition Diagram

    36. Increasing Performance • Processor performance can be measured by the rate at which it executes instructions • MIPS rate = f * IPC • f processor clock frequency, in MHz • IPC is average instructions per cycle • Increase performance by increasing clock frequency and increasing instructions that complete during cycle • May be reaching limit • Complexity • Power consumption

    37. Multithreading and Chip Multiprocessors • Instruction stream divided into smaller streams (threads) • Executed in parallel • Wide variety of multithreading designs

    38. Definitions of Threads and Processes • Thread in multithreaded processors may or may not be same as software threads • Process: • An instance of program running on computer • Resource ownership • Virtual address space to hold process image • Scheduling/execution • Process switch • Thread: dispatchable unit of work within process • Includes processor context (which includes the program counter and stack pointer) and data area for stack • Thread executes sequentially • Interruptible: processor can turn to another thread • Thread switch • Switching processor between threads within same process • Typically less costly than process switch

    39. Implicit and Explicit Multithreading • All commercial processors and most experimental ones use explicit multithreading • Concurrently execute instructions from different explicit threads • Interleave instructions from different threads on shared pipelines or parallel execution on parallel pipelines • Implicit multithreading is concurrent execution of multiple threads extracted from single sequential program • Implicit threads defined statically by compiler or dynamically by hardware

    40. Approaches to Explicit Multithreading • Interleaved • Fine-grained • Processor deals with two or more thread contexts at a time • Switching thread at each clock cycle • If thread is blocked it is skipped • Blocked • Coarse-grained • Thread executed until event causes delay • E.g.Cache miss • Effective on in-order processor • Avoids pipeline stall • Simultaneous (SMT) • Instructions simultaneously issued from multiple threads to execution units of superscalar processor • Chip multiprocessing • Processor is replicated on a single chip • Each processor handles separate threads

    41. Scalar Processor Approaches • Single-threaded scalar • Simple pipeline • No multithreading • Interleaved multithreaded scalar • Easiest multithreading to implement • Switch threads at each clock cycle • Pipeline stages kept close to fully occupied • Hardware needs to switch thread context between cycles • Blocked multithreaded scalar • Thread executed until latency event occurs • Would stop pipeline • Processor switches to another thread

    42. Scalar Diagrams

    43. Multiple Instruction Issue Processors (1) • Superscalar • No multithreading • Interleaved multithreading superscalar: • Each cycle, as many instructions as possible issued from single thread • Delays due to thread switches eliminated • Number of instructions issued in cycle limited by dependencies • Blocked multithreaded superscalar • Instructions from one thread • Blocked multithreading used

    44. Multiple Instruction Issue Diagram (1)

    45. Multiple Instruction Issue Processors (2) • Very long instruction word (VLIW) • E.g. IA-64 • Multiple instructions in single word • Typically constructed by compiler • Operations that may be executed in parallel in same word • May pad with no-ops • Interleaved multithreading VLIW • Similar efficiencies to interleaved multithreading on superscalar architecture • Blocked multithreaded VLIW • Similar efficiencies to blocked multithreading on superscalar architecture

    46. Multiple Instruction Issue Diagram (2)

    47. Parallel, SimultaneousExecution of Multiple Threads • Simultaneous multithreading • Issue multiple instructions at a time • One thread may fill all horizontal slots • Instructions from two or more threads may be issued • With enough threads, can issue maximum number of instructions on each cycle • Chip multiprocessor • Multiple processors • Each has two-issue superscalar processor • Each processor is assigned thread • Can issue up to two instructions per cycle per thread

    48. Parallel Diagram

    49. Examples • Some Pentium 4 • Intel calls it hyperthreading • SMT with support for two threads • Single multithreaded processor, logically two processors • IBM Power5 • High-end PowerPC • Combines chip multiprocessing with SMT • Chip has two separate processors • Each supporting two threads concurrently using SMT

    50. Power5 Instruction Data Flow