CSE 598 Nanoarchitectures Spring 2005 Lecture 1: Introduction

1. CSE 598 NanoarchitecturesSpring 2005Lecture 1: Introduction Vijay Narayanan (www.cse.psu.edu/~vijay)

3. What is Nanoscale?

4. Nanoscale Dimensions

5. Nanoscale Properties • A characteristic feature of moving to the nanometer scale (besides the growing domination of quantum physical effects) is that properties of surfaces or boundary layers play an increasing role compared with the bulk properties of the material. • Basic structures of nanotechnology are: • Pointlike structures smaller than 100 nm in all three dimensions (e.g. nanocrystals, clusters or molecules) • linear structures which are nanosized in two dimensions (e.g. nanowires, nanotubes and nanogrooves) • layered structures which are nanosized in only one dimension, "inverse" nanostructures (i.e. pores) and complex structures such as supramolecular units or dendrimers.

6. Nanoscale properties • The reduction of size into the nanometer area often results in characteristic properties of substances and materials which can be exploited for new applications and which do not appear in macroscopic pieces of the same materials. • significantly higher hardness and breaking strength • superplasticity at high temperatures • the emergence of additional electronic states • high chemical selectivity of surface sites • significantly increased surface energy

7. How to achieve Nanoscale Features? There are two fundamental strategies for penetrating the nanodimension. • "top-down" approach, which is predominant particularly in physics and physical technology. • Here,starting from microtechnology structures and components are more and more miniaturised. • "bottom-up/self-assembly" approach in which increasingly complex structures are specifically assembled from atomic or molecular components. • This approach is primarily featured in chemistry and biology, where dealing with objects of the nanometer scale has long been familiar practice.

8. Interdisciplinary by Nature • Nanotechnology requires a high degree of interdisciplinary and transdisciplinary cooperation and communication. This is due to the fact that at the nano level the terminology of physics, chemistry and biology overlaps and blurs, and also to the fact that techniques from a single discipline can or must be supplemented by techniques and expertise from other disciplines.

10. What we will cover in this class? • Nanoscale CMOS technologies • Process Variations, NonClassical CMOS Structures • Lithography Limits, Interconnect Challenges • Novel Memory Architectures • SEM, FeRAM, MRAM, PRAM • Nanosensor Architectures • Molecular Electronics • Spintronics and SET • Quantum Cellular Architectures • Carbon Nanotube Architectures • BioChips

11. Class Grading • Midterm Exam – 30% • Final Exam – 30% • Class Presentations and Project – 30% • Class Participation – 10%

12. Reference Books • Emerging Nanoelcetronics: Life with and after CMOS, Kluwer Academic Publishers • Several Research Papers • Books on Library Course Reserve in Pattee Library

13. CSE 598 NanoarchitecturesSpring 2005Lecture 2: Top 10 Challenges Vijay Narayanan (www.cse.psu.edu/~vijay)

14. Silicon’s Roadmap For a Cost-Performance MPU (L1 on-chip SRAM cache; 32KB in 1999 doubling every two years) Specification of what must be provided if Moore’s Law is to continue to hold. * clock rates double the SIA Roadmap http://www.itrs.net

15. Moore’s Law • No. of trans./chip doubles every generation (~18 mo.) • 100X increase in performance on SPECmarks in the last 10 years (from 33MHz 486 in 1990 to the 1.5GHz Pentium 4 in 2000) • 20X from technology scaling • 4X from architecture • 1.25X from compiler technology • How much longer can we track Moore’s Law ? Source: ISCA’01 Panel

16. Gate Length Scaling

17. Transistor Integration Capacity On track for 1B transistor integration capacity

18. I ≠0 I = 0 On I = 1ma/u I = ∞ I = 0 I ≠0 Off I = 0 I ≠ 0 Sub-threshold Leakage Is Transistor a Good Switch?

19. Hot Chips E (joules) = CL Vdd2 P01 + tsc Vdd Ipeak P01+ Vdd Ileakage P (watts) = CL Vdd2 f01 + tscVdd Ipeak f01 + Vdd Ileakage • Why worry about power consumption ? • determines battery life for mobile units and . . .

20. Challenge #1 Subthreshold Leakage

21. Sub-threshold Leakage Assume: 0.25mm, Ioff = 1na/m 5X increase each generation at 30ºC Sub-threshold leakage increases exponentially

22. SD Leakage Power SD leakage power becomes prohibitive

23. Leakage Power A. Grove, IEDM 2002 Leakage power limits Vt scaling

24. Challenge #2 Gate Leakage

25. 130nm Transistor CoSi2 Si3N4 Poly Si Gate Electrode 1.5 nm Gate Oxide 70 nm Si Substrate Gate Oxide is Near Limit Will high K happen? Would you count on it?

26. Gate Leakage Power If Tox scaling slows down, then Vdd scaling will have to slow down

27. Energy per Logic Operation Energy per logic operation scaling will slow down

28. Challenge #4 Variations

29. Low Freq Low Isb High Freq High Isb High Freq Medium Isb Frequency & SD Leakage 0.18 micron ~1000 samples 30% 20X

30. High Freq Medium Isb Low Freq Low Isb High Freq High Isb Vt Distribution 0.18 micron ~1000 samples ~30mV

31. Vdd & Temp Variation Temperature Variation (°C) Hot spots Heat Flux (W/cm2) Results in Vcc variation

32. Challenge #6 Economics

33. Litho Cost FAB Cost G. Moore ISSCC 03 www.icknowledge.com $ per Transistor $ per MIPS Exponential Costs

34. Fabrication Costs • Cost of building factories increases by a factor of two every three years; by 2010 a fab may cost $30 billion • Mask costs are growing rapidly adding more to upfront NRE for new designs • next-generation lithography methods require expensive complex masks (optical proximity correction (OPC) and phase shift (PSM)) that are computationally complex to generate and that have low error tolerances • multiple masks that require longer write times increase mask production costs

35. Exploding NRE’s • A mask set for a complex chip today can cost $500,000 (up from $100,000 a decade ago) • At 150nm SEMATECH estimates that we will be entering the regime of the $1M mask set • A 70nm ASIC will have $4M NRE ! Source: www.InnovationRevolution.com

36. Optical Lithography

37. Mask Costs

38. Optical Proximity Correction

39. Phase Shift Masks • Selectively altering the phase of the light passing through certain areas of a photomask in order to take advantage of destructive interference • improve resolution and depth of focus in optical lithography • Each aperture would transmit the light passing through in such a way that it would be 180 degrees out of phase from light passing though adjacent apertures. • Causes any overlapping light from two adjacent apertures to interfere destructively, thus reducing any exposure in the center ‘dark’ region. • This type of phase-shifting mask, known as an alternating aperture phase shift mask. • Most effective on device patterns which are highly repetitive and closely spaced, such as poly and metal layers.

40. Challenge #7 Slow Wires • Wire delay trends • Long wires don’t scale (RC delay) • constant delay for short wires (L scales down by S > 1) • Many “short wires” become “long wires” as technology scales • New microarchitectures typically increase wire lengths • accessing global resources • S > 1 and SG < 1 • for S = 1.15 and SG = 0.94, global wire delay goes up 50%

41. Semi-local wire resistance, scaled length Semi-local wire capacitance, scaled length Aggressive scaling Aggressive scaling 0.4 0.6 Conservative scaling Conservative scaling 0.3 0.4 pF Kohms 0.2 0.2 0.1 0 0 250 180 130 100 70 50 35 250 180 130 100 70 50 35 Technology Ldrawn (nm) Technology Ldrawn (nm) Scaling Module (Short) Wires • R is basically constant; C falls linearly with scaling Source: ISCA’01 Panel

42. Semi-global wire resistance, 1mm long Semi-global wire capacitance, 1mm long Aggressive scaling Aggressive scaling 0.4 0.6 Conservative scaling Conservative scaling 0.3 0.4 Kohms pF 0.2 0.2 0.1 0 0 0.25 0.18 0.13 0.1 0.07 50 35 250 180 130 100 70 50 35 Technology Ldrawn (nm) Technology Ldrawn (nm) Scaling Global (Long) Wires • R gets quite a bit worse; C is basically constant Source: ISCA’01 Panel

43. Clock Distribution Limits • Clocks are long wires with big RC’s that have rigid clock skew constraints Source: Matzke IEEE Computer

44. New Interconnect Technologies • Will new interconnect technologies save us? • Copper interconnect allows wires to be thinner without increasing their resistance, decreasing interwire and fringe capacitance • Low capacitance (low-k) dielectrics • SOI (silicon on insulator)

45. Signal Distribution Limits • Even if signals could be propagated at the velocity of light, there are finite wiring distribution limits • it would only be possible to distribute a signal over a 15mm radius with a 1GHz clock assuming a maximum skew of 5% • with a 10GHz clock that drops to 1.5mm radius

46. p T = t B T = # signal pins/chip t average # pins/block 0  p 1Rent exponent Normal values: 0.5  p  0.75 Challenge #8 Chip I/O Bottleneck • Limited signal pins • consume large number of pins in power/ground supplies (to combat the supply rail bounce) • what happens to Rent’s Rule ? Source: Landman, Russo, IEEETC, 1971

47. molecular scale Challenge #9 Reliability • Chip defects and transient errors will reduce the number of useful devices per unit area • use redundancy to work around chip defects, but • at the smallest device dimensions, transient errors due to • small number of electrons associated with each bit of information • thermal excitation of stray charge carriers, radioactive impurities, and cosmic rays may make it necessary to use redundancy on a massive scale (27-fold or even 81-fold) • Thermal densities will aggravate transient errors

48. Challenge #10 Design Costs • Microscopic issues • ultra-high speeds, clock distribution • power dissipation and supply rail drop • growing importance of interconnect • noise, crosstalk • reliability, manufacturability • Macroscopic issues • time-to-market • design complexity (millions of gates) • IP reuse • systems on a chip (SoC) • design verification • tool interoperability

49. The Productivity Gap 100000 10000 1000 100 10 1 0.1 0.01 58%/Yr compound Complexity growth rate Productivity (K) Trans./Staff-Mo. Logic Transistors/Chip (M) 21%/Yr compound Productivity growth rate * @ $ 150K/Staff Yr. (in 1997 Dollars) Source: SEMATECH

50. Limits to Terascale Integration • “Silicon technology has an enormous remaining potential to achieve terascale integration (TSI) . . . double-gate MOSfets with gate oxide thickness of ~ 1nm, channel widths of 3nm, and channel lengths of 10nm” Meindl, Science, Sept 2001 • “assuming the development and economical mass production of double-gate MOSfets. . . . The development of interconnecting wires for these transistors presents a major challenge to the achievement of nanoelectronics for TSI”