Towards Electronics for a Long Baseline Neutrino Detector

1. ν Towards Electronics for a Long Baseline Neutrino Detector Alfons Weber STFC & University of Oxford Alfons Weber

2. Alfons Weber Issues • Introduction • State of the Art • MINOS/OPERA • NOVA • T2K/MINERVA • Requirements • physics • photo detectors • R&D needs

3. Alfons Weber Introduction • There are N Detectors • At least 2N different electronics have been used to read them out • No unique solution • Solutions have been adapted from existing ASICS • driven by cost, timescale, physics. • not ideal • But get the job done

4. Alfons Weber Tensions • Near Detectors • high rate • beam synchronisation • limited channel count • Far Detectors • low rate • no beam signal available • huge channel count • Performance • high dynamic range, precise timestamps • 100% lifetime • low cost

5. Alfons Weber What the following is about • Electronics, need to integrate with • DAQ • photo detectors • Photo-detectors • PMT, APD, MPPC • DAQ • PCs? • Detector • scintillator with WLS fibre • large PMT arrays?

6. Alfons Weber Solution: MINOS ND • Based on existing QIE ASIC • dead-timeless for up to 20 μsec (spill) Input current 8-bit FADC value Analog Voltage QIE FADC FIFO 3 bit range code 2 bit CAP-ID code CAP-ID: QIE has 4 copies of current divider/integrator  4 capacitor IDs Every channel in the detector (9240) produces, every 18.87 nsec: {FADC, RANGE, CAP-ID} 1.4fC lowest count sensitivity, 16-bit effective dynamic range QIE output voltage Input charge

7. Alfons Weber Solution: MINOS ND (II) Timing System 8 MASTER crates 44 MINDER crates Front End (MINDER/MENUS) Readout (MASTER) Data Acquisition Analogue PMT Pulse Fast readout of digital data in response to trigger PVIC Transfers to PCs

8. Alfons Weber Solution: MINOS FD/OPERA • MINOS developed an ASIC chip for PMT readout with IDEAS • 32 channels VA32_HDR11 • shaping • amplification • sample & hold • output driver to ADC • Excellent product • fast shaping 500 nsec • noise < 2 fC • linear> 20 pC • 6 ASICs multiplexed onto 1 ADC

9. Alfons Weber PMTs Front End Electronics VFB VFB VFB 0 0 0 0 2 2 2 2 1 1 1 1 VFB HV HV HV HV VARC 1 VARC 2 VARC 0 VARC 2 VARC 1 VARC 0 VME Readout Crates VME VME 2.5 MB/s serial serial DAQ LAN DAQ LAN TRC ROP TRC ROP Ether. Ether. PVIC PVIC 0 3 15 0 2 3 Optical PVIC Bus RC Branch Readout Processors 1 B R P B R P B R P B R P DAQ LAN Timestamp Clock 1 sec GPS ticks antenna 40 Mbytes/s PVIC Bus DAQ LAN DAQ LAN TP N TP 0 TP 1 DCP Timing Central unit Trigger Processors Timing PC GPS To Persistent Store To Dispatcher 10-100 Kbytes/s Timing System Solution: MINOS FD (system) • Trigger-less DAQ system • ASIC close to PMT • ADC in VME crate • fast PVIC-bus to PC trigger farm • search for hits correlated in space and time • Timing System • Absolute time from GPS(tabs= 200 nsec) • optical distribute along large detector (trel= 4 nsec)

10. Alfons Weber 4.2µs 4.2µs 4.2µs 58ns 58ns 58ns 58ns 58ns 58ns 58ns 58ns 58ns 540ns 540ns 540ns 540ns 540ns 540ns 540ns 540ns Solution: T2K/280m & MINERVA • 8 (15) batches • Separated by 540 (241) nsec • charge integrated in batches Spill Structure 2-3.53s 2-3.53s Bunch Structure Chip Time Structure integration reset

11. Alfons Weber TRIP-t Front-end architecture • only preamp gain affects signal feeding discriminator • no fine control (x1 or x4) • discriminator threshold Vth • common to all channels on chip • analogue bias settings • gain, Vth, etc. • programmable via serial interface preamp gain adjust 1,2,3,…8 very simplified – neglecting features not relevant to ND280 operation integrate/reset Qin analogue pipeline 1pF 3pF discriminator x10 gain = 1 or 4 disc. O/P Vth reset

12. Alfons Weber Solution: T2K (System Overview) SiPM63 SiPM0 SiPM63 SiPM0 SiPM63 SiPM0 … … … TFB0 TFB1 TFB47 … TPS Trigger Primitives Power distribution Clk & trg data CTM RMM0 Cosmic trigger Gigabit/Ethernet Clk & trg Clk & trg Acronyms:TFB: TRIP-t front-end boardRMM: r/o merger moduleCTM: global trigger moduleMCM: master clock moduleSCM: slave clock moduleTPS: TRIP-t power supplyFPN: front-end proc. node (PC) Gigabit/Ethernet MCM SCM FPN Clk & trg Special trigger GPS 1Hz/100MHz (Acc. RF) Gigabit/Ethernet Spill trig & # Gigabit/Ethernet

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15. Alfons Weber Solution: NOvA

16. Alfons Weber Common Thread • Different solutions for near and far detectors • developed around different existing ASICs • heavy use of FPGAs • huge variation in cost • $20 - $300 per channel • DAQ and electronics can’t be developed independently • later solutions move towards commercial back ends

17. Alfons Weber Requirements • high QE photo detectors • bigger detectors  cheaper • low noise electronics • low readout thresholds  bigger detectors • dynamic range • limited? 1:1000 • Timing • O(1nsec) • low trigger threshold • low and high rate environment ?

18. Alfons Weber Requirements (II) • Will take a long time for community to settle on • detector • photo detector • requirements • Try to develop multi-purpose ASIC • test beam • near detector • external trigger, limited lifetime • far detector • cheap, scalable, ~100% lifetime, self-triggering

19. Alfons Weber Ingredients • ADC • 1:1000 • TDC • 1 nsec • Trigger • local/global • clock distribution • cheap HV supply • 30-1000 V • monitoring • commercial interfaces

20. Alfons Weber The Pass • Resume • Performance is not leading edge • Cost is main driving factor • multi purpose device • Work needed • requirements capture • design multi-purpose readout system • Electronics • DAQ • Develop ASIC • develop test system

21. Alfons Weber Who and Where? • Who is driving this? • which community • physicists vs. electronics engineers • Where can the work be done? • major labs • Universities • Has to be user driven. • Many questions, few answers.