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Computer Components & Function. Week 2. Objectives. Identify on the basic structures used for computer components interconnection. Understand the requirements for a computer to perform an operation. Von Neumann Architecture. Data and instructions are stored in a single read-write memory
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Objectives • Identify on the basic structures used for computer components interconnection. • Understand the requirements for a computer to perform an operation
Von Neumann Architecture • Data and instructions are stored in a single read-write memory • The memory contents are addressable by location • Execution occurs in a sequential fashion (unless using explicit modifications) from one instruction to the next 3 key concepts
Hardwired vs Programmed Sequence ALU Data Results (a) ‘Programming’ in Hardware Instruction Codes Instruction Intepreter Control Signals General purpose ALU Data Results (b) Programming in software
Program Concept • Hardwired systems are inflexible • General purpose hardware can do different tasks, given correct control signals • Instead of re-wiring, supply a new set of control signals
What is a program? • A sequence of steps • For each step, an arithmetic or logical operation is done • For each operation, a different set of control signals is needed
Function of Control Unit • For each operation a unique code is provided • e.g. ADD, MOVE • A hardware segment accepts the code and issues the control signals
Components • The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit • Data and instructions need to get into the system and results out • Input/output • Temporary storage of code and results is needed • Main memory
Instruction Cycle • Two steps: • Fetch • Execute
Fetch Cycle • Program Counter (PC) holds address of next instruction to fetch • Processor fetches instruction from memory location pointed to by PC • Increment PC • Unless told otherwise • Instruction loaded into Instruction Register (IR) • Processor interprets instruction and performs required actions
Execute Cycle • Processor-memory • data transfer between CPU and main memory • Processor-I/O • Data transfer between CPU and I/O module • Data processing • Some arithmetic or logical operation on data • Control • Alteration of sequence of operations • e.g. jump • Combination of above
Example of Program Execution • Consider a simple hypothetical machine with the below characteristics • 16-bit Instruction format with 4-bit opcode • Partial opcode list • 0001 = Load AC from memory • 0010 = Store AC to memory • 0101 = Add to AC from memory How many different opcodes can this machine contain? How many addressable memories can this machine access? Opcode Address
Example of Program Execution Using the simple fetch and execute cycle, illustrate the partial program execution showing relevant portions of memory and processor registers AC (accumulator), PC (program counter) and IR (instruction register) for the following : Add the contents of memory at memory location 940 with contents of memory location 941 and stores it back into memory location 941. Assume the partial execution stored program is at 300 Question.. So how many fetch and execute cycle is required for this partial program execution?
Instruction Cycle : State Diagram details • Instruction address calculation : Determine the address of the next instruction to be executed. • For example if the register is 16-bits long and the memory address is organized in 16-bit words, then add 1 to the previous address. If the register is separated as individual addressable 8-bit bytes, then add 2 to the previous address. • Instruction fetch : Read instruction from the memory location into the processor • Instruction operation decoding : Analyze the instruction to determine the type of operation need to perform and operand(s) to be used
Instruction Cycle : State Diagram details Operand address calculation : Determines the address of operands whether in memory address or I/O addresses. This happens only when an operation involves references of operands. Operand fetch : Fetch the operand from memory or read from I/O Data operation : Perform the operation indicated in the instruction Operand store : Write the result into memory or send to I/O
Interrupts • Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing • Program • e.g. overflow, division by zero • Timer • Generated by internal processor timer • Used in pre-emptive multi-tasking • I/O • from I/O controller • Hardware failure • e.g. memory parity error
Interrupt Cycle • Added to instruction cycle • Processor checks for interrupt • Indicated by an interrupt signal • If no interrupt, fetch next instruction • If interrupt pending: • Suspend execution of current program • Save context into STACK (memory) • Set PC to start address of interrupt handler routine (interrupt Vector) • Process interrupt • Restore context and continue interrupted program
Transfer of Control via Interrupts Interrupt Vector
Multiple Interrupts • Disable interrupts • Processor will ignore further interrupts whilst processing one interrupt • Interrupts remain pending and are checked after first interrupt has been processed • Interrupts handled in sequence as they occur • Define priorities • Low priority interrupts can be interrupted by higher priority interrupts • When higher priority interrupt has been processed, processor returns to previous interrupt
