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IEEE 2007 report Part II G.Villani

IEEE 2007 report Part II G.Villani. >1500 participants Nuclear Science & Medical Imaging Detectors and RO Electronics development. NSS section Trend on detectors Noise studies on sub-micron devices. 2007. 2006. OTHERS. 3D. CCD. DRIFT. OTHERS. 3D. CCD. CMOS. DRIFT. CMOS.

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IEEE 2007 report Part II G.Villani

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  1. IEEE 2007 report Part II G.Villani G.Villani

  2. >1500 participants • Nuclear Science & Medical Imaging • Detectors and RO Electronics development • NSS section • Trend on detectors • Noise studies on sub-micron devices 2007 2006 OTHERS 3D CCD DRIFT OTHERS 3D CCD CMOS DRIFT CMOS G.Villani

  3. Recent developments on deep N-well CMOS MAPS with sparsification capability Giuliana Rizzo INFN and University, Pisa on behalf of SLIM5 Collaboration 2007 IEEE Nuclear Science Symposium Honolulu, October 27-November 3 2007 G.Villani

  4. PRE SHAPER DISC LATCH Recent developments on deep N-well CMOS MAPS with sparsification capability Principle of operation • The undepleted epitaxial layer acts as a potential well for electrons • Signal (~1000 e-) collected through diffusion by the n-well contact • Charge-to-voltage conversion provided by the sensor capacitance  small collecting electrode • Simple in-pixel readout (additionals nwells for PMOS not allowed in standard MAPS design!)  sequential readout • Full in-pixel signal processingrealized exploiting triple well CMOS process • Deep nwell (DNW) as collecting electrode • Gain independent of the sensor capacitance collecting electrode can be extended • Area of the “competitive” nwells inside the pixel kept to a minimum:, they steel signal to the main DNW electrode. • Fill factor = DNW/total n-well area ~90% in the prototype test structures • Pixel structure compatible with data sparsification architecture to improve readout speed. Original concept proposed by RAL ~ 4 years ago Design and characterization of a novel, radiation- resistant active pixel sensor in a standard 0.25 m CMOS technology G.Villani

  5. APSEL2M APSEL2T APSEL0 APSEL1 TEST_STRUCT Preamplifier characteriz. Cure thr disp. and induction Accessible pixel Study pix resp. ST 130 Process characterization APSEL2_CT APSEL2_90 APSEL2D Submitted DNW MAPS Chips 130 nm ST Sub. 8/2006 Sub. 9/2006 Sub. 12/2004 Sub. 8/2005 Improved F-E 8x8 Matrix ST 90nm characterization Sub. 11/2006 Sub. 5/2007 Sub. 7/2007 Sub. 7/2007 APSEL3D APSEL3_T1, T2 G.Villani Test chips to optimize pixel and FE layout 8x32 matrix. Shielded pixel Data Driven sparsified readout Test digital RO architecture Test chips for shield, xtalk

  6. 90Sr electrons S/N=14 Landau mV Cluster signal (mV) APSEL2 3x3 matrix: analog output 3x3 matrix, full analog output 50 mm pixel pitch Cluster Multiplicity 1 2 Noise events properly normalized Hit pixels in 3x3 matrix • Noise ENC = 50 e- • Indications of small cluster size (1-2 pixels) • Cluster Signal for MIP (Landau MPV) 700 e- •  S/N = 14 Cluster seed G.Villani

  7. Noise Vthr APSEL2 8x8 matrix: digital output Noise scan: hit rate vs discriminator threshold 8x8 matrix digital output Sequential readout Vth (mV) Threshold dispersion ~ 100 e- 90Sr electrons: single pixel spectrum Differential spectrum from digital output Spectrum from analog output Noise (mV) Average Noise ENC = 50 e- G.Villani

  8. Fast Readout Architecture for MAPS • Data-driven readout architecture with sparsification and timestamp information under development. • In the active sensor area we need to minimize: • the logical blocks with PMOS to minimize the competitive nwell area and preserve the collection efficiency of the DNW sensor. • digital lines for point to point connections to allow scalability of the architecture with matrix dimensions and to reduce cross talk with the sensor underneath. MP 4x4 pixels See Poster N24-260 Data lines in common • Matrix subdivided in MacroPixel (MP=4x4) • with point to point connection to the • periphery readout logic: • Register hit MP & store timestamp • Enable MP readout • Receive, sparsify, format data to output bus 2 MP private lines Column enable lines in common Periphery readout logic • APSEL2D chip received in July, tests started • Pixel response and noise as expected • Readout seems to work as expected, but crosstalk is present and interfering with operations Data out bus G.Villani

  9. Cross talk between digital lines and substrate Requires aF level parasitic extraction to be modeled Relatively small S/N ratio (about 15) Especially important if pixel eff. not 100% Power dissipation 60 mW/pixel Creates significant system issues M6 Digital routing (local/global) M5 Shield (VDD/GND) M4 M3 Analog routing (local) M2 M1 From APSEL2 to APSEL3 APSEL2 issues APSEL3D Digital lines shielding APSEL3 Redesigned front-end/sensor Optimize FE Noise/Power: • Reduce sensor capacitance (from 500 fF to ~300 fF) keeping the same collecting electrode area • reduce DNW sensor/analog FE area (DNW large C) • Add standard NWELL area (lower C) to collecting electrode. • New design of the analog part Optimize sensor geometry for charge collection efficiency using fast simulation developed: • Locate low efficiency region inside pixel cell • Add ad hoc “satellite” collecting electrodes APSEL3 Power=30 mW/pixel: Perfomance APSEL3 expected performance G.Villani

  10. An example of sensor optimization • With old sensor geometry (left) Efficiency ~ 93.5% from simulation (pixel threshold @ 250 e- = 5xNoise) • Inefficient regions shown with dots (pixel signal < 250 e-) • Cell optimized with satellite nwells (right) Efficiency ~ 99.5% 3x3 MATRIX sensor optimized 3x3 MATRIX old sensor geom Satellite nwells connected to central DNW elect Competitive Nwells DNW collecting electrode G.Villani

  11. Conclusions & Perspectives • DNW MAPS design (130 nm, triple well STM CMOS technology) looks very promising for application in future thin trackers with fast readout requirements. • Latest DNW MAPS (APSEL2) structures, with optimized noise and threshold dispersion, showed good sensitivity to ionizing radiation (soft X and beta). • New improvements in noise, power, charge collection efficiency implemented in the APSEL3 series (just received). • Digital crosstalk can be kept under control using metal shield between sensor and digital lines. • Data driven readout architecture with sparsification and timestamp under development: 8x32 matrix produced, 32x128 matrix in production by end Nov. 2007. • Test beam foreseen in summer 2008 to measure DNW MAPS rate capability, efficiency, resolution. • DNW MAPS sensors, developed within the SLIM5 Collaboration, now considered by the SuperB and ILC communities for application in their silicon vertex trackers. • Contacts: giuliana.rizzo@pi.infn.it G.Villani

  12. A Photogate Monolithic ActivePixel Sensor with Lateral ElectricField to Improve Its ChargeTransfer-Efficiency G.Villani

  13. A Photogate Monolithic Active Pixel Sensor with Lateral Electric Field motivation for photogate: • why classical MAPS are not • the optimum solution? • • SNR at the limit, almost no margin for • increase of noise; possible sources are numerous: Ileak, power supply, etc., • • large charge diffusion for single small charge collecting diode; • • attenuation of signal due to Cconv increase for bigger or more diodes per pixel. • Photogate: • large coverage of active area; • large conversion factor; G.Villani

  14. A Photogate Monolithic Active Pixel Sensor with Lateral Electric Field • Standard photogate: • Electrons collected distribute evenly under the gate; • Surface states trap electrons, decreasing efficiency G.Villani

  15. A Photogate Monolithic Active Pixel Sensor with Lateral Electric Field • Enhanced photogate: • potential difference allows electrons drift under the gate; • less trapping, increased efficiency G.Villani

  16. A Photogate Monolithic Active Pixel Sensor with Lateral Electric Field • Simulations photogate: • 3D model used for simulation • E-field cut @ 5nm below SiO2 interface • Charge collected vs. bias G.Villani

  17. A Photogate Monolithic Active Pixel Sensor with Lateral Electric Field Test structure TSMC 0.25um Tests started October 2007 Laser source and Fe55 Test structure no laser G.Villani Test structure with laser Test structure with Fe55

  18. A Photogate Monolithic Active Pixel Sensor with Lateral Electric Field • Conclusions • Applying potential difference between opposite ends of the photogate proved to prompt charge transfer (surface transport) either to: • one end of the photogate (where it waits for closing transfer gate) or • directly to the sensitive node (where it can be probed via i.e. source follower). • Both photogate options, viz. with and without • transfer gate allow CDS, although: • It can be done within one access for pixel with • transfer gate (INT, RO, TXon, RO, RST, TXoff... ), • It is required to store two full frames in memory • and to do CDS after the readout of the second frame • is accomplished (RST, RO, INT, RO,... ), . • The improved photogate may be considered • for applications, where « big pixels » are required, • i.e. central tracker @ ILC instead of TPC (Si pixel • tracker proposed by Chris Damerell ALCPG 2007) • Contacts: deptuch@ieee.org G.Villani

  19. Development of 3D Detectors for Very High Luminosity Colliders • Celeste Fleta • University of Glasgow • October 30, 2007 • On behalf of the CERN-RD50 Collaboration G.Villani

  20. This talk shows a review of the work of RD50 on the use of 3D detectors as trackers in high radiation environments 1. The CERN-RD50 collaboration 2. Silicon 3D detectors 3. Simulation work 4. Different approaches • Single sided 3D • Double sided 3D • Full 3D G.Villani

  21. 3D detectors • Proposed by S. Parker et al. NIMA395 (1997). • 3-d array of p and n electrodes that penetrate into the detector bulk • Lateral depletion • Maximum drift and depletion distance set by electrode spacing • Thicker detectors possible • Reduced charge sharing • Reduced collection time and depletion voltage • Technologically complex Rad hard 3D planar G.Villani

  22. Simulation study of 3D sensors P-type FZ trap model • University of Glasgow • Modified Perugia 3-level trap model • Trap parameters modified to match experimental trapping times • Model accuracy assessed by comparing with results from planar devices [D. Pennicard et al., 10th RD50 Workshop, June 2007] (Data from M. Lozano et al., IEEE Trans. Nucl. Sci., vol. 52 (2005)) G.Villani

  23. Single type column detectors (ITC-irst) • 2-stage depletion • Lateral depletion • Planar-like depletion towards the back contact (Confirmed with C-V and CCE measurements, see Scaringella et al., NIMA 579 (2007)) Electrons swept away by transversal field and drift to nearest column (~40 µm) Holes drift in central region and diffuse/drift to p+ contact (~300-500 µm) • Fabricated by ITC-irst/CNM • Strip, pad detectors • 300 or 500 µm p-type substrate • Hole depth 130-150 µm, diameter ~10 µm • Columns not filled, just passivated • Variation of the STC-3D developed at BNL • Ohmic contact is implemented on the same side of the column etching: true one-sided detector (backside not processed) G.Villani

  24. Position resolved CCE in STC-3D strip detectors Vbias = 20V • Laser tests with ATLAS SCT readout • University of Freiburg • 40MHz ATLAS SCT EndCap electronics • Binary readout • Shaping time 20ns • Laser spot 4-5µm, penetration 100µm • STC-3D AC coupled strip detector ~25% signal drop Vbias = 80V • Lateral depletion ~20V • Non-homogenous response: low field region in interstrip area • Results after irradiation and with β source in S. Kuehn’s talk (N44-2) G.Villani

  25. CCE in STC-3D irradiated strip detectors • Position sensitive TCT measurements in Ljubljana (see poster N24-150 ) • IR laser, FWHM ~7µm • STC-3D DC coupled detector, 64 x 10 columns • 80µm pitch, 80µm between holes CCE after neutron irradiation 25ns transient current integration [G.Kramberger et al., 10th RD50 Workshop, June 2007] • As expected, STC-3D are not radiation hard: • E-field determined by doping (higher doping large E). • When the volume between columns is fully depleted, the electric field cannot be increased further • Essential to counteract trapping • Very non-homogenous response due to variations in the electric field (saddle in mid-region) G.Villani

  26. (p+) n-Si Double sided 3D detectors • Proposed by IMB-CNM (Spain) • Electrodes etched from opposite sides of the wafer • Double side processing • No sacrificial wafer is required • IMB-CNM currently processing a first run of n-type wafers with Medipix2, Pilatus2 and strip detectors • Double-sided technology also being investigated by ITC-irst  see talk N18-3 27.5m G.Villani

  27. Double sided 3D detectors • Short charge collection times because both carrier types mainly drift horizontally • High drift velocity as the electric field can be increased even after full depletion. • Disadvantages: low field region below columns No damage 1016 neq/cm2 • 250µm columns both devices • DS-3D has slightly higher collection at low damage (greater device thickness!) • But at high fluence, results match standard 3D Undepleted 100V bias Performance comparable to standard 3D G.Villani

  28. Full 3D detectors • Project Glasgow/Diamond Light Source Synchrotron to develop 3D detectors for X-ray diffraction experiments • Fabrication by IceMOS Technology Ltd. (Northern Ireland) • Full 3D detectors on n-type Si • Prototype 3D detectors will be integrated and tested with existing r/o electronics: • Medipix2, Pilatus2, Beetle readout chips • Readout in p-electrodes  hole collection • All contacts on the top  need to route metal lines connecting all n-electrodes (biasing) • Fabrication: start with a thick (~500 μm) wafer, create electrodes from the top (~250 μm), then grind/polish to expose electrodes. G.Villani

  29. Conclusions • Ongoing work of RD50 in 3D detectors • Promising candidates as vertex sensors for extreme radiation environments • Low depletion voltage, good charge collection even for s-LHC irradiation levels • STC-3D detectors fabricated and tested succesfully • Simple fabrication process, useful to tune in the technology and gain experience with testing methods • Long charge collection times, can be used in experiments that do not need a fast response • Double sided and full 3D available soon • More information: http://rd50.web.cern.ch/RD50/ G.Villani

  30. Minimum Noise Design of Charge Amplifiers with CMOS Processes in the 100 nm Feature Size Range L. Rattia,c, M. Manghisonib,c, V. Reb,c, V. Spezialia,c, G. Traversib,c aUniversità degli Studi di Pavia bUniversità degli Studi di Bergamo cINFN Pavia IEEE Nuclear Science Symposium and Medical Imaging Conference November 2 2007 – Honolulu, Hawaii, USA G.Villani

  31. Motivation Device scaling has enabled the use of CMOS processes in the fabrication of high performance front-end circuits for radiation detectors Continuous miniaturization meets the demand for increasedspatial resolution, denserfunctional packing and higherionizing radiation hardness set by the experiments at the next generation colliders (LHC upgrade, ILC, Super B-Factory) Constant technology monitoring is necessary to study scaling effects on the main design parameters oppose process obsolescence keep design criteria and methodologies up to date CMOS processes in the 100 nm feature size range now being considered for the design of analog front-end circuits G.Villani

  32. Content Noise performance analysis in analog front-end channels based on experimental characterization of devices from a 130 nm and a 90 nm CMOS technologies HCMOS9 - 130 nm CMOS090 - 90 nm VDD=1.2 V tOX=2 nm COX=15 fF/mm2 VDD=1 V tOX=1.6 nm COX=18 fF/mm2 Focused on front-end design for pixel and microstrip detectors under low power dissipation constraints All the interesting design parameters – input devicebias condition, dimensions and polarity, peaking time, detector capacitance – taken into account Emphasis on second order effects and scaling related phenomena Analysis of total ionizing dose(TID) effects in view of applications to harsh environments G.Villani

  33. Model of charge measuring system CD=detector capacitance+strays reset network CF=feedback capacitance Cin=input capacitance tp=peaking time CF shaper T(stp)=shaper transfer function T(stp) en 1 detector Qd charge preamplifier CD in Cin In a charge sensitive amplifier (CSA), noise performance are mostly dependent on the input device noise features Noise in the detector leakage current and in the reset network not considered G.Villani

  34. G S D IGS IGD IGC • series 1/f noise • technology dependent contribution • both kf and αf depend on the polarity of the DUT (af,s=0.85 for NMOS, 1.05÷1.2 for PMOS) • series white noise • channel thermal noise Model of the charge measuring system • Kf 1/f noise parameter • αf slope-related parameter • kB Boltzmann’s constant • T absolute temperature • αw excess noise coefficient • γ channel thermal noise coefficient • n proportional to the subthreshold ID-VGS slope • gm transconductance reset network CF shaper T(stp) en en 1 detector Qd charge preamplifier CD in Cin • parallel 1/f noise • 1/f noise in the gate current • parallel white noise • full shot noise in the gate current • q elementary charge • Ij contributions to the gate current (IGC, IGS and IGD) • Kf,G 1/f noise parameter • af,G slope-related parameter (~0.9) • DL gate-source/drain overlap G.Villani

  35. en in Equivalent noise charge The ENC equation includes: a series (white and 1/f) noise related contribution • A1 and A2(af) are shaping coefficients • Cin and Sw depend on input device bias condition, dimensions and polarity • Af depends only on gate dimensions in NMOS devices; it depends also on bias conditions in PMOS devices • 1/f noise contribution to the ENC is peaking time dependent a parallel (white and 1/f) noise related contribution • A3 and A4(af,G) are shaping coefficients • Sw,G and Af,G depend on input device bias condition, dimensions and polarity The results presented here have been obtained in the case of an RC2-CR shaping stage following the CSA G.Villani

  36. Noise in 90nm CMOS process Gate current no longer negligible in processes with sub-3 nm gate oxide thickness due to direct tunneling Sizeable parallel noise contribution found in 90 nm devices In CSAs, parallel white noise may provide a significant ENC contribution already at tp=100 ns Contribution from parallel 1/f noise mostly negligible G.Villani

  37. Optimum ENC and Width in 90nm CMOS Optimum ENC achieves its minimum value at a peaking time of a few hundreds of ns and rises again due to white parallel noise contribution Optimum width peaks at tp100 ns, then decreases due to gate current, and parallel noise,dependence on W G.Villani

  38. VD IGD VD related effects in 90nm CMOS FE Changes in the ENC at tp>100 ns due to drain voltage related variations in the gate current Minimum is achieved at VDG=0, when IGD=0. TRIODE G.Villani

  39. TID effects in 90 nm NMOS input front-end Significant ENC variations (about 20% at tp=100 ns) only in the peaking time range where series 1/f noise is predominant Virtually no changes in the extreme regions of the explored range  no significant TIDeffects on white series and parallel noise Assuming a 100 mm thick detector • S/N from 11 tp 10 @ tp=10 ns • S/N form 28 to 23 @ tp=100 ns 90 nm appears to be harder than 130 nm process V. Re et al., “Impact of lateral isolation oxides on radiation-induced noise degradation in CMOS technologies in the 100 nm regime”, 2007 NSREC Conference, to be published in IEEE TNS G.Villani

  40. Conclusion Results from front-end design optimization in 130 nm and 90 nm CMOS technologies for application to pixel and microstrip detector readout have been presented Optimization procedure takes into account second order effects and scaling related phenomena Kf dependence on overdrive voltage in PMOS devices parallel contribution due to the noise in the input device gate current dependence of the parallel noise contribution on the drain voltage in the input device Data from TID characterization were used to predict preamplifier performances in harsh environment The proposed model provides a comprehensive tool which can be easily extended to other ultra deep submicron technologies Use of high K gate insulators may modify radiation hardness and noise properties in next CMOS nodes Contacts: lodovico.ratti@unipv.it. G.Villani

  41. V P C on IEEE 2007 • Overall always interesting (the most comprehensive and attended conference on electronic aspects of NSS); • However not many novel or new solutions in terms of detections or readout; • RAL established presence with novel solutions presented every year ( serial powering system, novel CMOS detectors, improved CCD… just from PPD); • Low power solutions becoming increasingly important. G.Villani

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