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Mastering EDA Algorithms: Course Overview & Problems Preview

Explore Electronic Design Automation tools, algorithms & problems in this course. Gain skills for IC designs & EDA field careers. Study routing, partitioning & floorplanning tasks. Join Bilkent University's Computer Engineering Dept.

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Mastering EDA Algorithms: Course Overview & Problems Preview

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  1. Course Overview Mustafa Ozdal Mustafa Ozdal Computer Engineering Department, Bilkent University

  2. What is EDA? • Stands for Electronic Design Automation • a.k.aVLSI CAD • Software tools to support engineers in the creation of new IC designs. • EDA tools significantly reduce the cost and time-to-market of new projects. • A CPU can easily contain > 1B transistors in a single chip • Manual design is prohibitive Mustafa Ozdal Computer Engineering Department, Bilkent University

  3. What is EDA? • Solves a wide-range of problems high-level system design to fabrication (and everything in between) • Strong software skills required • This course will cover the physical design problems • Abstract and algorithmic problems • No EE knowledge needed Mustafa Ozdal Computer Engineering Department, Bilkent University

  4. Why Study EDA Algorithms? • You may consider a career in the EDA field • EDA companies: Synopsys, Cadence, Mentor Graphics, … • Design companies: Intel, IBM, Apple, AMD, Nvidia, TI, Qualcomm, ARM, TSMC, … • You may be working in a related field • e.g. Computer architecture: What is the hardware cost, energy cost, etc. of a new feature? • e.g. Scientific computing: Common algorithms used in both domains (e.g. graph partitioning, clustering, etc.) • You may want to improve your algorithmic skills • We will study algorithms for abstract problems that also occur in other domains. e.g. routing, rectangle packing, partitioning, etc. Mustafa Ozdal Computer Engineering Department, Bilkent University

  5. Course Overview • Schedule: Lecture: Tue. 13:40-14:30 EA502 Lecture: Thu. 15:40-17:30 EA502 Spare Hour: Tue. 14:40:15:30 • Course project: More in-depth study of a topic • Literature survey + implementation + experiments • Presentation (survey + plans) • Final report (implementation + experiments + conclusions) Mustafa Ozdal Computer Engineering Department, Bilkent University

  6. Sneak Preview of the Problems Mustafa Ozdal Computer Engineering Department, Bilkent University

  7. Partitioning Problem Circuit: 1 3 2 7 8 4 6 5 Partition the netlist into 2 equal parts (i.e. each part must have 4 gates) such that the # of edges between two partitions is minimized.

  8. Partitioning Problem Circuit: Cut cb 1 3 2 7 8 4 6 5 Cut ca Block A Block B Block A Block B 5 4 1 8 3 4 1 8 5 2 7 3 2 6 6 7 Cut ca: four external connections Cut cb: two external connections How to do this for > 1M gates?

  9. Floorplanning Problem Example Given: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2 Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1 Task: Floorplan with minimum total area enclosed B C C B A A 4 B 3 C A A

  10. Floorplanning Problem Example Given: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2 Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1 Task: Floorplan with minimum total area enclosed

  11. Floorplanning Problem Example Given: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2 Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1 Task: Floorplan with minimum total area enclosed Solution: Aspect ratiosBlock A with w = 2, h = 2; Block B with w = 2, h = 1; Block C with w = 1, h = 3 This floorplan has a global bounding box with minimum possible area (9 square units). How to do this for 1000s of blocks?

  12. A Placement E D C B F Which is better? A C E E D F B D F A C B More wirelength Harder routing Less wirelength Easier routing

  13. Placement as an Optimization Problem • Place all cells in the netlist such that: • Minimize chip area • Minimize wire length • Make routing easy • Satisfy timing constraints • Keep cells on critical paths closer • Satisfy various other design constraints • A typical design can have > 1M cells • NP-complete problem

  14. Routing Problem Netlist: Placement result N1 = {C4, D6, B3} N2 = {D4, B4, C1, A4} N3 = {C2, D5} N4 = {B1, A1, C3} 3 4 C 1 A 1 2 4 1 3 Technology Information (Design Rules) B 4 5 6 4 D

  15. Routing Problem Netlist: N1 = {C4, D6, B3} N2 = {D4, B4, C1, A4} N3 = {C2, D5} N4 = {B1, A1, C3} 3 4 C 1 A 1 2 4 N1 1 3 Technology Information (Design Rules) B 4 5 6 4 D

  16. Routing Problem Netlist: N1 = {C4, D6, B3} N2 = {D4, B4, C1, A4} N3 = {C2, D5} N4 = {B1, A1, C3} 3 4 C 1 A 1 2 4 N4 N2 N3 N1 1 3 Technology Information (Design Rules) B 4 5 6 4 D How to do this for > 1M nets?

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