Investigation for Readout Electronics of WAC in LHAASO

1. Investigation for Readout Electronics of WAC in LHAASO Shubin Liu University of Science & Technology of China April 22nd, 2009

2. LHAASO Project for γs and CRs WCD: 4x2.25x104m2 μ : 100x400m2 e : 2400x1m2 CT: 28 BD: 1000x1m2 AS+μ: ARGO: 104m2 Large High Altitude Air Shower Observatory USTC, Shubin Liu

3. Water Cherenkov Detector • Sensitive to cosmic gamma rays around TeV • Maintaining the all-sky, high-duty-factor capabilities of an EAS array • 4 ponds each with the area of 2.25x104m2 • Each will be filled with purified water • 900 PMTs will be deployed under the water of Each pond • For a total of 3600 PMTs and corresponding readout electronics • Hamamatus R5912 employed in Daya Bay experiment is the candidate type USTC, Shubin Liu

4. The Requirement of Readout Electronics • Digitalizing the accurate time of arrival of the selected showers • Both the timing and pulse height of each PMT is important • 1ns time resolution for leading edge time measurement • A wide dynamic range of 1~4000 PEs for pulse height measurement • A trigger decision must be made to select showers • Clock and calibration systems are essential • Distributing the large number of signals over the long distance (~100m) is an issue • Pre-Amplifier or Front-end process circuit is needed USTC, Shubin Liu

5. Sketch of Electronics USTC, Shubin Liu

6. Two Candidate Scheme • Traditional scheme • Similarly with Daya Bay Experiment’s electronics, with the additional Pre-amplifier • The mature scheme • Much power consumption and expense because of the ADCs • TOT scheme • Adopted by Milagrito/Milagro and the planned Hawk Experiment • The TDC marks each time that a pulse crosses a voltage threshold with a edge • Lower power consumption and expense for the absence of ADCs USTC, Shubin Liu

7. Traditional Readout Scheme • Patch panels (FEBs) above the water accommodating the Pre-Amplifiers, which are fed by the PMT signals via the 5m long cables, and drive the ~100m long cables to the digital boards • Two amplifiers and corresponding shaping and ADC circuits for the wide dynamic range (1~4000PE) • Waveform digitalization by high speed (40MHz) ADCs to find the peak of the waveform after shaping • Fast discriminator provides the arriving time of the pulse, recorded by TDC, and fed to the trigger logic USTC, Shubin Liu

8. Charge Measurement in Daya Bay Experiment • The wide dynamic range (1~4000PE), and high charge measurement resolution (0.1PE), are achieve in this scheme • The PMT signal with a pulse width of about 10-20ns is sent to a high speed amplifier • The amplified signal is then fed to the CR-(RC)4 shaping circuits with different gain parameters • The simulation shows error of lower than 4% can be achieved with the ADC sampling speed of 40MHz • Two 12-bit ADCs are employed to sampling these two signals at a speed of 40MHz • Results in a number of ~7200 ADCs to the number of ~3600 PMT channels • ~700mW/chip and ~￥300/chip USTC, Shubin Liu

9. Charge measurement in Detail USTC, Shubin Liu

10. Time Measurement in Daya Bay Experiment • A fast discriminator generates the timing pulse • The threshold is defined by a DAC set via VME interface • The leading edge of the output represents the arrival time of the signal • The trigger signal deriving from trigger system is used as the stop signal • The TDC is built on a high-performance FPGA • Two ultra high speed gray-code counters change at different phases of 1/2 a clock cycle • Time precision of 1.5625ns and STD Error about 0.7ns can be achieved USTC, Shubin Liu

11. TOT Scheme • The cable from PMT comes out of the pond and goes into the Front End Boards (FEB) • The signal from each PMT is split and sent to high gain and low gain charge amplifiers, followed by a pair of discriminators with different PE thresholds • The leading edge gives the pulse’s arrival time information, and the time which the amplified PMT signal spends over the low/high threshold represents the charge of the signal • The FEB accommodate several neighboring PMTs’ process circuits • The digital signals carry the time information of the pulses to the digital board via a long ribbon cable USTC, Shubin Liu

12. Concept of TOT • The pulse height of a signal from PMT is proportional to the stored charge caused by photoelectrons • A PMT pulse delivers a charge which charges a capacitor • The capacitor then discharges as that in a simple RC circuit • The leading edge gives the time information and the length of the pulse gives the logarithm of the charge USTC, Shubin Liu

13. The Conceptual Simulation for TOT USTC, Shubin Liu

14. The Conceptual Simulation for TOT • The time over threshold is proportional to the logarithm of the PE number • Small signal with little amount PEs results in the large error • Amplification and low threshold discriminator for small signal are essential • While amplification for large signal will lead to saturation USTC, Shubin Liu

15. Two Separate Thresholds Discriminator Concept • A small pulse from the PMT can pass only the low threshold, and thus it only produces two crossing edge times • A large signal can fire both the low threshold and the high threshold to generate 4 edge counts in the TDC • The delays in the circuit ensure a fixed time interval (~25ns) between the low and high threshold outputs USTC, Shubin Liu

16. The Advantages of Dual Threshold TOT • Achieve the wide dynamic range of charge measurement • The signals which are large enough intend to saturate the high gain amplifier • Alleviate the influence of Pre-pulsing • A large PMT pulse with sufficiently large amount PEs increases the incidence of pre-pulsing which affects the low TOT value as well as the low start time • High-start slewing is not influenced by pre-pulsing, so using the high-start slewing whenever it is possible is always the first choice • Differentiate between overlapping pulses • A long pulse will never be mistaken for a large signal if the high threshold does not fire USTC, Shubin Liu

17. TOT Circuit in Detail USTC, Shubin Liu

18. The Conceptual Simulation for Dual Threshold TOT PMT R5912 signal pattern provided by Daya Bay Experiment's American Cooperator The high gain channel is followed by a disc. wiht low threshold at 1/4 PE The low gain channel is followed by a disc. wiht high threshold at 5 PEs USTC, Shubin Liu

19. The Conceptual Simulation for Dual Threshold TOT USTC, Shubin Liu

20. The Conceptual Simulation for Dual Threshold TOT PMT R5912 signal pattern acquired in Daya Bay Experiment The high gain channel is followed by a disc. wiht low threshold at 1/4 PE The low gain channel is followed by a disc. wiht high threshold at 5 PEs USTC, Shubin Liu

21. The Conceptual Simulation for Dual Threshold TOT USTC, Shubin Liu

22. TDC Built on FPGA Prototype • Based on the coarse-fine architecture consisted of the coarse counter and the time-coding delay line interpolator • TDC built on FPGA achieves the precision of ~50ps (LSB) and STD error better than 25ps USTC, Shubin Liu

23. TDC Built on FPGA Cable Delay Test Setup USTC, Shubin Liu

24. The Advantages of TOT • A large amount of money is saved • Two times of channels of ADCs are not needed • The cheaper ribbon cable takes place of the coaxial cable • With the absence of ADC data, the event size is cut significantly, and in turn the ability to handle a higher trigger rate in the data acquisition is enhanced • The ADC conversion time is relatively slow and that may cause dead time during data taking • There is no need to worry about synchronizing the ADC • TDC data and the TOT has much better dynamic range than that in the ADC • Alleviate the influence of Pre-pulsing USTC, Shubin Liu

25. Calibration Apparatus • Based on the laser - fiber-optic – diffusing ball concept • Adopted by Milagro/Milagrito • Calibration for slewing corrections and time offsets USTC, Shubin Liu

26. Trigger Logic • Multiplicity trigger: If the number of PMT signals crossing the threshold in 200ns is higher than the setting number (20), the trigger is generated, and the information from the event is processed • For each PMT signal that crosses the threshold, the corresponding electronics channel generates a logic pulse with 200 ns wide and a fixed amplitude • The analog sum of all these fixed width pulses is sent to a discriminator • If the analog sum is higher than the threshold setting, the trigger signal is generated USTC, Shubin Liu

27. Clock Distribution • Analogous with Daya Bay Experiment’s clock system USTC, Shubin Liu

28. Schedule • Both traditional and TOT scheme are in progress • After the concept simulation, the schematic design and PSPICE simulation has been started • The first version of traditional scheme preamplifier is planned to be test in Daya Bay experiment circumstance USTC, Shubin Liu

29. Thanks! USTC, Shubin Liu