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Arria 10 Transceivers at 9.6 Gbps

This article discusses a possible issue with Arria 10 transceivers operating at 9.6 Gbps, including information on PLLs and alternative modes for achieving the desired speed.

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Arria 10 Transceivers at 9.6 Gbps

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  1. Arria 10 Transceivers at 9.6 Gbps Erno DAVIDWigner Research Center for Physics (HU) 17 February, 2016

  2. Possible Issue with Arria 10 Transceivers at 9.6 Gbps? • The source of this issue: • In Kintex 7 there is a documented GTX Gap between 8.01 and 9.79 Gbps which is related to PLLs • http://www.in2p3.fr/actions/formation/Numerique12/XILINX_HighSpeedTransceivers_IN2P3.pdf#page=29 • Is the same PLL related issue is presented in the Arria 10? • The answer is: NO • We need 4.8 GHz for the 9.6 Gbps line speed for 10G PON and this is fully supported by the Arria 10 PLLs (CMU PLL, fPLL, ATX PLL) • Is there any other issue @ 9.6 Gbps? • Yes: The “Standard PCS” mode supports only 8.9 Gbps in speed grade -3 • As a workaround we plan to use the “Direct PCS” (PMA only) mode and implement the PON related PCS functionality in fabric • We have a preliminary implementation and we think that this approach is viable 2

  3. Xilinx 7 Series Transceiver Architecture Line Rate Coverage (-3E speed grade) http://www.in2p3.fr/actions/formation/Numerique12/XILINX_HighSpeedTransceivers_IN2P3.pdf#page=29 3

  4. Altera Arria 10 (Transceiver Performance for Arria 10 GX/SX Devices) Source: Arria 10 Device Datasheet (2016.02.11) Page 27 4

  5. Altera Arria 10 (Transmit PLL Recommendation Based on Data Rates) Source: Arria 10 Transceiver PHY User Guide (2016.02.11) Page 404 • This is a new recommendation from the UG (2016 Feb) • In earlier documentation there was no range recommendation and we choose ATX PLL for GBT-FPGA implementation due to the best jitter performance • Now we should reevaluate our decision and investigate the ATX PLL usage and understand the situation 5

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