Non-Uniform Cache Architectures for Wire Delay Dominated Caches. Abhishek Desai Bhavesh Mehta Devang Sachdev Gilles Muller. Plan. Motivation What is NUCA UCA and ML-UCA Static NUCA Dynamic NUCA Simulation Results. Motivation. Bigger L2 and L3 Caches are needed Programs are larger
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Data residing closer to the processor is accessed much faster than data that reside physically farther from the processor
The closest bank in a 16MB on-chip L2 cache built in 50nm process technology could be accessed in 4 cycles, while an access to the farthest bank might take 47 cycles.
Avg. access time: 11/41 cycles
Avg. access time: 255 cycles
Avg. access time: 34 cycles
Area: Wire overhead 20.9%
and decoderS-NUCA-1 cache design
Avg. access time: 24 cycles
Area: Channel overhead 5.9%
and decoderS-NUCA-2 cache design
Avg. access time: 18 cycles
8 bank sets
Policy on miss:
D-NUCA has the following plus points: