Mitigation of Single Event Upset (SEU)
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Mitigation of Single Event Upset (SEU) by Virtual Redundancy in Design. Paper No. E3. Kaijie Wu Polytechnic University [email protected] Jake Karrfalt Alternative System Concepts, Inc [email protected] This work is supported by: BMDO (contract # DASG60-01-C-0073) ,

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Mitigation of Single Event Upset (SEU) by Virtual Redundancy in Design

Paper No. E3

Kaijie Wu Polytechnic University

[email protected]

Jake Karrfalt Alternative System Concepts, Inc

[email protected]

This work is supported by: BMDO (contract # DASG60-01-C-0073),

JHU Applied Physics Laboratory, Atmel and ASC

Wu, Karrfalt


Purpose

A CED technique that uses the virtual redundancy in design will be presented and a case study is discussed.

Purpose

Wu, Karrfalt


Outline

Describe the idle cycles based CED technique. will be presented and a case study is discussed.

Describe the RC6 encryption algorithm

Implement RC6 encryption data path using the idle cycles based CED.

Outline

Wu, Karrfalt


The idea of idle cycles based ced

A1 will be presented and a case study is discussed.

A2

A3

M1

M2

M3

C1

C2

C3

C4

×

C5

Check Board of idle cycles

The idea of idle cycles based CED:

+1

+1

A1

A1

+4

+2

+3

+4

+2

+3

A2

A1

A3

A2

A1

A3

+3

+3

*1

*1

M1

A3

A2

M1

*4

*2

*3

*4

*2

*3

M2

M1

M3

M2

M1

M3

*5

*3

*3

*5

M2

M3

M1

M1

Non-CED design

CED design

Wu, Karrfalt


Symmetric block cipher structure
Symmetric Block Cipher will be presented and a case study is discussed.Structure

User Key

Key Schedule

Round Key

Encryption

Decryption

Cipher

Text

Plain

Text

Plain

Text

Round 1

Round 1

Round N

Round N

Wu, Karrfalt


Rc6 encryption algorithm
RC6 Encryption Algorithm will be presented and a case study is discussed.

Input: 128-bit plain text stored in four,

32-bit registers A,B,C,D

round keys S[0], S[1], S[2], .., S[43]

Output: 128-bit cipher text stored in A,B,C,D

B = B + S[0]; D = D + S[1] --pre whitening

for i = 1 to 20 do --whitening

{ t = (B*(2B+1)) <<< 5; u = (D*(2D+1)) <<< 5;

A = ((A xor t) <<< u) + S[2i];

C = ((C xor u) <<< t) + S[2i +1];

(A, B, C, D) = (B, C, D, A) }

A = A + S[2r+2]; C = C + S[2r+3]; --post whitening

Wu, Karrfalt


Implementation of rc6 round operation

will be presented and a case study is discussed.

+

+

<<<

<<<

+

+

Implementation of RC6 round operation

B

D

C

A

<<<5

<<<5

<<<5

XOR

XOR

<<<5

<<<

S(2r)

<<<

S(2r+1)

+

+

C

A

Wu, Karrfalt


Data path of rc6 encryption algorithm
Data path of RC6 will be presented and a case study is discussed.encryption algorithm

input

+

×

×

<<<

+

Register

Register

Register

+

×

×

<<<

+

keys

keys

C0,

C41

C1,

C3,

C39

C2,

C4,

C40

20 rounds

Wu, Karrfalt


Idle cycles of rc6 data path

M1 will be presented and a case study is discussed.

M2

O1

O2

×

×

C1

C2

<<+

<<+

×

×

C3

C4

<<+

<<+

×

×

C5

C6

<<+

<<+

Idle cycles of RC6 data path

M1

M2

O1

O2

×

×

C1

×

×

C2

<<+

<<+

×

×

C3

<<+

<<+

×

×

C4

<<+

<<+

×

×

C5

<<+

<<+

×

×

C6

<<+

<<+

Wu, Karrfalt


Ced data path of rc6 encryption
CED data path of RC6 will be presented and a case study is discussed.encryption

c

Register

Register

input

+

×

×

<<

+

Register

Register

Register

+

×

×

<<

+

key

key

C0,

C41

C1,

C3,

C39

C2,

C4,

C40

20 rounds

Wu, Karrfalt


Fault injection

OR will be presented and a case study is discussed.

AND

Fault Injection

input

input

Fault Injection

Control Bit

Fault Injection

Control Bit

Component

Component

Output

Output

Inject stuck-at-1 fault

Inject stuck-at-1 fault

Wu, Karrfalt


Fault injection study
Fault injection study will be presented and a case study is discussed.

Clock

Fault in

input register

Result of

computation

3

2

Result of

recomputation

1

Error Indication

Wu, Karrfalt


Fault simulation result
Fault simulation result will be presented and a case study is discussed.

Wu, Karrfalt


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