1 / 47

Interface

Interface. 8088 I/F with basic IO, RAM and 8255. Topics. Timing diagram Address Bus, R/W, Data Memory Map I/O Address Decoding CPU is addressable lager than devices. Chip Supports TTL : De-multiplexer, Latch, Buffer. Timing Diagram : Read Cycle. Timing Diagram : Write Cycle.

acacia
Download Presentation

Interface

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Interface 8088 I/F with basic IO, RAM and 8255

  2. Topics • Timing diagram • Address Bus, R/W, Data • Memory Map I/O • Address Decoding • CPU is addressable lager than devices. • Chip Supports • TTL : De-multiplexer, Latch, Buffer

  3. Timing Diagram: Read Cycle

  4. Timing Diagram: Write Cycle

  5. BUS Buffering and Latching

  6. Basic Architecture Dr.Jim Plusquellic, University of Maryland, Baltimore County http://www.csee.umbc.edu/~plusquel/310/

  7. Bus Architecture • Address: • If I/O, a value between 0000H and FFFFH is issued. • If memory, it depends on the architecture: • 20 -bits (8086/8088) • 24 -bits (80286/80386SX) • 25 -bits (80386SL/SLC/EX) • 32 -bits (80386DX/80486/Pentium) • 36 -bits (Pentium Pro/II/III)

  8. Bus Architecture • Data: • 8 -bits (8088) • 16 -bits (8086/80286/80386SX/SL/SLC/EX) • 32 -bits (80386DX/80486/Pentium) • 64 -bits (Pentium/Pro/II/III) • Control: • Most systems have at least 4 control bus connections (active low). • MRDC (Memory ReaD Control), MWRC , IORC (I/O Read Control), IOWC

  9. Bus Standards • ISA (Industry Standard Architecture): 8 MHz • 8-bit (8086/8088) • 16-bit (80286-Pentium) • EISA : 8 MHz • 32-bit (older 386 and 486 machines). • PCI (Peripheral Component Interconnect): • 33 MHz 32-bit or 64-bit (Pentiums) • VESA (Video Electronic Standards Association): • 32-bit or 64-bit (Pentiums), Runs at processor speed. • Only disk and video. Competes with the PCI but is not popular.

  10. Bus Standards • USB (Universal Serial Bus): • 12 Mbps / 480 Mbps, Serial connection to microprocessor. • For keyboards, the mouse, modems and sound cards. To reduce system cost through fewer wires. • IEEE 1394 • 400 Mbps, primary target is audio/visual consumer electronic devices • AGP (Advanced Graphics Port): 66MHz • 64-bits for 533MB/sec, Fast parallel connection, video cards. To accommodate the new DVD (Digital Versatile Disk) players.

  11. Memory : Blank Layout

  12. Memory : Blank Layout

  13. Memory : Blank Layout

  14. Basic I/O Architecture

  15. Interrupt Vector: DOS PC

  16. IO Space

  17. Basic I/O Interface : Input

  18. Basic I/O Interface : Output

  19. I/O Port Decoding

  20. MEMORY

  21. Memory Types • Two basic types: • ROM: Read-only memory • RAM: Read-Write memory • Four commonly used memories: • ROM • Flash (EEPROM) • Static RAM (SRAM) • Dynamic RAM (DRAM)

  22. Memory Chips • The data pins are typically bi-directional in read-write memories. • The number of data pins is related to the size of the memory location. For example, an 8-bit wide (byte-wide) memory device has 8 data pins. • Each memory device has at least one chip select (CS) or chip enable (CE) or select (S) pin that enables the memory device. • This enables read and/or write operations. • If more than one are present, then all must be 0 in order to perform a read or write.

  23. SRAM vs. DRAM • SRAMs • SRAMs used for caches have access times as low as 10ns . • DRAMs • SRAMs are limited in size (up to about 128Kb). • DRAMs are available in much larger sizes, e.g., 64M X 1. • DRAMs MUST be refreshed every 2 to 4 ms • Since they store their value on an integrated capacitor that loses charge over time.

  24. Memory Address Decoding

  25. Memory Address Decoding • The processor can usually address a memory space that is much larger than the memory space covered by an individual memory chip. • In order to splice a memory device into the address space of the processor, decoding is necessary. • For example, the 8088 issues 20-bit addresses for a total of 1MB of memory address space.

  26. Ex. Memory Address Decoding • The BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins. • A decoder can be used to decode the additional 9 address pins and allow the EPROM to be placed in any 2KB section of the 1MB address space.

  27. Ex. Memory Address Decoding • To determine the address range that a device is mapped into:

  28. Ex. Memory Address Decoding • This 2KB memory segment maps into the reset location of the 8086/8088 (FFFF0H). • NAND gate decoders are not often used. Rather the 3-to-8 Line Decoder (74LS138) is more common.

  29. 3-to-8 Line Decoder • G2A, G2B, and G1 must be active. • Each output of the decoder can be attached to an 2764 EPROM ( 8K X 8 ).

  30. EPROM 2764 x 8

  31. More on Address Decoding • Yet a third possibility is a PLD (Programmable Logic Device). • PLDs come in three varieties: • PLA (Programmable Logic Array) • PAL (Programmable Array Logic) • GAL (Gated Array Logic) • A PAL example (16L8) is commonly used to decode the memory address, particularly for 32-bit addresses generated by the 80386DX and above.

  32. PLD as address decoder • AMD 16L8 PAL decoder. • It has 10 fixed inputs (Pins 1-9, 11), two fixed outputs (Pins 12 and 19) and 6 pins that can be either (Pins 13-18).

  33. 8088 Memory Interface • The memory systems "sees" the 8088 as a device with: • 20 address connections (A19 to A0). • 8 data bus connections (AD7 to AD0). • 3 control signals, IO/M, RD, and WR. • Interfacing the 8088 with: • 32K of EPROM (at addresses F8000H-FFFFFH). • 512K of SRAM (at addresses 00000H-7FFFFH).

  34. 8088 Memory Interface: EPROM

  35. 8088 Memory Interface: EPROM • The EPROM will also require the generation of a wait state. • The EPROM has an access time of 450ns . • The 74LS138 requires 12ns to decode. • The 8088 runs at 5MHz and only allows 460ns for memory to access data. • A wait state adds 200ns of additional time

  36. 8088 Memory Interface: RAM

  37. 8088 Memory Interface: RAM • The 62256s on the previous slide are actually SRAMs. Access times are on order of 10ns . • Flash memory can also be interfaced to the 8088. However, the write time ( 400ms !) is too slow to be used as RAM.

  38. 8088 I/F with Programmable Peripheral Interface 8255 Part I

  39. PPI : 82C55 • The 82C55 is a popular interfacing component, that can interface any TTL-compatible I/O device to the microprocessor. • It is used to interface to the keyboard and a parallel printer port in PCs (usually as part of an integrated chipset). • Requires insertion of wait states if used with a microprocessor using higher that an 8 MHz clock. • PPI has 24 pins for I/O that are programmable in groups of 12 pins and has three distinct modes of operation. • In the PC, an 82C55 or its equivalent is decoded at I/O ports 60H-63H.

  40. 8255 Block Diagram

  41. Pin layout of 8255

  42. Interfacing 8255 PPI

  43. That’s all

More Related