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EVLA Monitor and Control

EVLA Monitor and Control. Module Interface Board (MIB) Design. MIB Block Diagram. Embedded Controller. Infineon TRICore TC11IB  System On a CHIP  12 MHZ External Clock  1.5 MBytes RAM  Hardware/Software Resets Watchdog Timer Sleep Modes Seven Thirty-Two Bit Timers.

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EVLA Monitor and Control

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  1. EVLA Monitor and Control Module Interface Board (MIB) Design EVLA Monitor & Control Hardware PDR March 13, 2002

  2. MIB Block Diagram EVLA Monitor & Control Hardware PDR March 13, 2002

  3. Embedded Controller • Infineon TRICore TC11IB  System On a CHIP 12 MHZ External Clock 1.5 MBytes RAM  Hardware/Software Resets • Watchdog Timer • Sleep Modes • Seven Thirty-Two Bit Timers EVLA Monitor & Control Hardware PDR March 13, 2002

  4. Embedded Controller • Infineon TC11IB – Interfaces  Media Independent Interface (MII) • PCI Bus – Version 2.2 @33MHz • MultiMediaCard Interface • Two Asynchronous Serial Ports • One Synchronous Serial Port (SPI) • Standard External Bus Interface EVLA Monitor & Control Hardware PDR March 13, 2002

  5. Ethernet Interface • Ethernet Interface – 100 MBit/second  Translation Chip – Intel LXT971A  Fiber Optic Transceiver – Infineon V23809-C8-C10 EVLA Monitor & Control Hardware PDR March 13, 2002

  6. Flash Memory • Flash Memory – Checksum  Code Storage  MIB – Boots Main Operation Code  Device – Device Specific Code  Parameter Storage  MIB – Loads Slot ID and Parameters  Device – Device Parameters  All Code Documented EVLA Monitor & Control Hardware PDR March 13, 2002

  7. Data Storage Memory • Data RAM – Inside TC11IB  Code Storage  Parameter Storage  Communication Data Storage EVLA Monitor & Control Hardware PDR March 13, 2002

  8. Reset Logic • Reset Logic  Power Supervisor – Maxim MAX706  Watchdog Protection – TC11IB  Devices Must Reset into Safe Condition EVLA Monitor & Control Hardware PDR March 13, 2002

  9. Timing Logic • Timing Logic  19.2 Hz Timing Signal (Transition)  1 PPS Timing Signal  10 Second Timing Signal  10 ms Timing Signal  Devices May Require Precise Timing  Hardware Timing EVLA Monitor & Control Hardware PDR March 13, 2002

  10. Parallel Interface • Parallel Interface  Thirty-Two Bits Transfer  PCI Bus  External Bus EVLA Monitor & Control Hardware PDR March 13, 2002

  11. Serial Interfaces • Serial Interfaces  Asynchronous Ports  One Two Wire Port  One Modem Port  Synchronous Ports  SPI Port – UP to Sixteen Bits  How are Select Lines Provided? EVLA Monitor & Control Hardware PDR March 13, 2002

  12. Address Logic • Address Logic  Memory Mapped Functions  Devices  Multiplexed Address/Data Bus  Separate Address/Data Bus EVLA Monitor & Control Hardware PDR March 13, 2002

  13. Control Logic • Control Logic  Peripheral Interfaces  Motorola or Intel or Both  NRAO Generated Interface  VLBA Model  Dual Port RAM Model EVLA Monitor & Control Hardware PDR March 13, 2002

  14. A/D or D/A Logic • A/D or D/A Logic  A/D Logic  Device  D/A Logic  Device EVLA Monitor & Control Hardware PDR March 13, 2002

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