VLSI Design Reconfigurable Computing ENG60903 Advanced Topics in VHDL Stephen Coe Guangfa Lu Friday, March 07,

1. 1 VLSI Design & Reconfigurable Computing ENG*6090(3) Advanced Topics in VHDLStephen CoeGuangfa LuFriday, March 07, 2003

2. 2 VHDL Presentation Brief introduction to VHDL structure Entity Architecture Structural/Data Flow/Behavioral descriptions What is it Syntax Special Cases File I/O Declaration Open/Close Textio Test Benches What are they How to use examples

3. 3 VHDL Presentation Aliases What are aliases for? Object Aliases How to simplify complex data structure with aliases. Signature Non-object Aliases Subprograms Similar idea to other programming language Parameter modes Functions Procedures Generics and Configurations Motivation How to use them

4. 4 VHDL �VHDL� is a acronym which stands for VHSIC Hardware Description Language �VHSIC� stands for Very High Speed Integrated Circuits The purpose of this programming language is to assist circuit designers to describe the characteristics of circuit. As you all know, VHDL is a acronym which stands for VHSIC hardware decriptive language. The purpose of this language is to assist designers with designing complex circuitsAs you all know, VHDL is a acronym which stands for VHSIC hardware decriptive language. The purpose of this language is to assist designers with designing complex circuits

5. 5 How VHDL Looks Each section of VHDL code is broken down into two parts The entity which describes the interface and how the component or circuit interacts with the outside world The architecture which describes the function of the component or circuit There are two parts to VHDL code structure. The entity and the architecture. The entity decribes how the circuit is interaced with the outside world. The architecture describes the functionality of the circuit (what it does)There are two parts to VHDL code structure. The entity and the architecture. The entity decribes how the circuit is interaced with the outside world. The architecture describes the functionality of the circuit (what it does)

6. 6 The Entity entity latch is port (s,r: in bit; q, nq: out bit); end latch; Here is the syntax for the entity of program. The first line includes the name of the entity. This is often a one name description of the circuit. The second line describes what are the inputs to the circuit and the third line shows the output of the circuit. A graphical representation is found in the bottom left cornerHere is the syntax for the entity of program. The first line includes the name of the entity. This is often a one name description of the circuit. The second line describes what are the inputs to the circuit and the third line shows the output of the circuit. A graphical representation is found in the bottom left corner

7. 7 The Architecture This next slide shows the syntax for the architecture. The first line holds a description of the architecture as well as the name of the entity that the architecture belongs to. The description can be anything, although often it describes the type of definition used. Between the begin and the end of the structure holds the functionality of the circuit. A graphical representation is shown in the bottom left corner.This next slide shows the syntax for the architecture. The first line holds a description of the architecture as well as the name of the entity that the architecture belongs to. The description can be anything, although often it describes the type of definition used. Between the begin and the end of the structure holds the functionality of the circuit. A graphical representation is shown in the bottom left corner.

8. 8 Description types VHDL can be structured in three different ways. Structural Data flow Behavioral Usually, a mixture of all three methods are used in the design of the circuit In VHDL, there are three different ways to describe the architecture of a circuit. They are Structural description, Dataflow description and Behavioral Description. Often when programming in VHDL, a combination of all three of theses methods are used in the design. In VHDL, there are three different ways to describe the architecture of a circuit. They are Structural description, Dataflow description and Behavioral Description. Often when programming in VHDL, a combination of all three of theses methods are used in the design.

9. 9 Structural Description Structural description uses text to show how components of a circuit are put together similar to a schematic capture approach to designing a circuit It is to combine smaller blocks or predefined components into a larger circuit by describing the way that the blocks interact The structural method is similar to a block diagram smaller components are used to make a circuit without knowing what is happening in the block It can be thought of as a netlist A netlist is used to describes how components are connected together form a circuit A structural description is a way to textually show how components of a circuit are put together. It is similar to a schematic capture approach where components (such as AND, OR gates) are linked together in a certain way. A structural description is similar to a block diagram of the circits, it shows how the components are put together without worrying about how the components work. It also can be thought of as a net list.A structural description is a way to textually show how components of a circuit are put together. It is similar to a schematic capture approach where components (such as AND, OR gates) are linked together in a certain way. A structural description is similar to a block diagram of the circits, it shows how the components are put together without worrying about how the components work. It also can be thought of as a net list.

10. 10 Structural Syntax entity latch is port (s,r: in bit; q, nq: out bit); end latch; architecture structure of latch is component nor_gate port (a,b: in bit; c: out bit); end component; begin n1: nor_gate port map (r, nq, q); n2: nor_gate port map (s=>a, q=>b, nq=>c); end structure; This is a simple example of a latch to demonstrate a structural description. Since we are talking about a structural description, structural is placed in the architecture description section. The component pin specification is used to show how the pins are laid out for the component. The pin specification is a copy of the entity for that component. It should be noted that all the components are declared between the architecture and the begin statements. Port map is used to show how the signals, from the entity or internal signals, are connected to the different pins on the component. QUESTIONSThis is a simple example of a latch to demonstrate a structural description. Since we are talking about a structural description, structural is placed in the architecture description section. The component pin specification is used to show how the pins are laid out for the component. The pin specification is a copy of the entity for that component. It should be noted that all the components are declared between the architecture and the begin statements. Port map is used to show how the signals, from the entity or internal signals, are connected to the different pins on the component. QUESTIONS

11. 11 Description Representation This slide is a graphical representation of the code on the previous slide. Everything inside the read box is part of the architecture and the everything within the yellow shows the entity pins.This slide is a graphical representation of the code on the previous slide. Everything inside the read box is part of the architecture and the everything within the yellow shows the entity pins.

12. 12 Internal Signals It is also possible to use internal signals to the architecture These are signals that are only used for connectivity within the architecture. This would be used if two components inputs and outputs are connected together without being connected to any pin described in the entity They are defined between the architecture line and the begin line Another thing that should be noted is internal signals. Thes are signals that are used to connect components together within the architecture. For example in the diagram, there are two half adders that need to be connected together without being connected to any of the signals in the entity statement. Internal signals are defined in between the architecture statement and the begin statement, similar to the component declaration.Another thing that should be noted is internal signals. Thes are signals that are used to connect components together within the architecture. For example in the diagram, there are two half adders that need to be connected together without being connected to any of the signals in the entity statement. Internal signals are defined in between the architecture statement and the begin statement, similar to the component declaration.

13. 13 Advantages of Structural description Hierarchy allows for the simplification of the design Component Reusability allows the re-use of specific components of the design (Latch, Flip-flops, half-adders, etc) Some of the advantages of structural design is it promotes hierarchy, allowing for a complex circuit to be broken down into smaller components. It also allows for reusability of these components. Once you have designed the components once, you can use theses components multiple times within your design. Each component is design independent. This means that you can replace or test each component without affecting the overall structure of the circuit.Some of the advantages of structural design is it promotes hierarchy, allowing for a complex circuit to be broken down into smaller components. It also allows for reusability of these components. Once you have designed the components once, you can use theses components multiple times within your design. Each component is design independent. This means that you can replace or test each component without affecting the overall structure of the circuit.

14. 14 Data Flow Data flow describes how the data flows through the circuit, from input to output It uses built in functions to describe the flow of data All commands in Data flow are concurrent (occur at the same time) Data flow operates in discrete time, when changes occur on the input, it immediately affects the output of the circuit This method is like the more traditional way of designing a circuit using gates For some traditional hardware designers, it is easier to use the data flow method, since it deals with the traditional method of designing circuits. The next section to be discussed is the data flow description. Dataflow basically just describes how the signals flow through the circuit from input to output. Usually it uses built in functions (such as AND or OR) to describe how the data flows. All dataflow descriptions are concurrent. This means that they all happen at the same time. They also operate in descrete time (no delays). A change on the input instantly changes the output. Data flow is thought of as a traditional way of designing a circuit, which is why may older hardware designers like this method better.The next section to be discussed is the data flow description. Dataflow basically just describes how the signals flow through the circuit from input to output. Usually it uses built in functions (such as AND or OR) to describe how the data flows. All dataflow descriptions are concurrent. This means that they all happen at the same time. They also operate in descrete time (no delays). A change on the input instantly changes the output. Data flow is thought of as a traditional way of designing a circuit, which is why may older hardware designers like this method better.

15. 15 Data Flow Syntax entity latch is port (s,r: in bit; q, nq: out bit); end latch; architecture dataflow of latch is begin q<= r nor nq; nq<= s nor q; end dataflow; This slide shows the syntax for dataflow descriptions. The architecture description is of type dataflow and it betlongs to the entity latch. The logical data assignment is showing that the data is dlowinf from the right hand side to the left hand side. The signal operator is used show that it is a signal assignment. Questions. This slide shows the syntax for dataflow descriptions. The architecture description is of type dataflow and it betlongs to the entity latch. The logical data assignment is showing that the data is dlowinf from the right hand side to the left hand side. The signal operator is used show that it is a signal assignment. Questions.

16. 16 Behavioral Descriptions Unlike the other two methods for describing the architecture, behavioral description is like a black box approach to modeling a circuit It is designed to do a specific task, how it does it is irrelevant It is used to model complex components which are hard to model using basic design elements Behavioral is often more powerful and allows for easy implementation of the design Most texts they combine both data flow and behavioral descriptions into one The last description method mentioned is the behavioral method. Unlike the other methods, the behavioral method is though of as a black box approach to programming VHDL. The system is programmed to do a specific task, but how this task is done is left up to the compiler. This method is more powerful than the other methods, since it allows for easy implementation of complex circuits. Although most text combine dataflow and behavioral into one since they are both describing the behavior of the circuit.The last description method mentioned is the behavioral method. Unlike the other methods, the behavioral method is though of as a black box approach to programming VHDL. The system is programmed to do a specific task, but how this task is done is left up to the compiler. This method is more powerful than the other methods, since it allows for easy implementation of complex circuits. Although most text combine dataflow and behavioral into one since they are both describing the behavior of the circuit.

17. 17 Behavioral description Behavioral descriptions are supported inside a process statement A process is used to describe complex behaviors of the circuit The contents of a process can include sequential statements These sequential statements are similar to commands in conventional programming languages (it, for, etc) which can only be used in the body of a process statement Although, inside a process is sequential, the process itself is concurrent, all processes in a architecture begin execution at the same time The process statement is declared in the body of the architecture in the same way as signal assignments in data flow Processes are used within behavioral descriptions. These processes are declared within the body of the architecture. A process is used to describe the complex behavior that make behavioral descriptions so powerful. All statements within a process are executed sequentially (they are executed from top to bottom). This allows for special sequential statements (if, for, while, etc) to be used within the process. Although inside a process is sequential, the process statements themselves are concurrent. This means that if there are multiple processes within one architecture, all processes begin at the same time.Processes are used within behavioral descriptions. These processes are declared within the body of the architecture. A process is used to describe the complex behavior that make behavioral descriptions so powerful. All statements within a process are executed sequentially (they are executed from top to bottom). This allows for special sequential statements (if, for, while, etc) to be used within the process. Although inside a process is sequential, the process statements themselves are concurrent. This means that if there are multiple processes within one architecture, all processes begin at the same time.

18. 18 Elements of a Process Processes can have a list of signals that they depend on, a sensitivity list, or they can use wait signals to make the process wait for a event to occur (not both) They are only execute if the signals in the sensitivity list change This makes it critical to ensure that the signals that the process depends on are in the sensitivity list Each process is executed once upon power up of the system Wait statements are similar to sensitivity lists, but have the advantage of forcing a process to wait at any point within the process, not just the beginning. A process is dependent on a sensitivity list of wait statements (but not both). The sensitivity list is a list of signals that must change in order for a process to execute. This makes it critical to ensure that all the necessary signals are included in the sensitivity list, otherwise the process might not execute when needed. It should also be noted that each process is executed once upon powering up the system. A wait statement is similar to the sensitivity list with a couple of extra advantages. A wait statement can be placed anywhere withing the body of a process, and there is no limit to the number of wait statements that can be used within one process. A wait statement can wait on a specific signal, length of time or a Boolean expression.A process is dependent on a sensitivity list of wait statements (but not both). The sensitivity list is a list of signals that must change in order for a process to execute. This makes it critical to ensure that all the necessary signals are included in the sensitivity list, otherwise the process might not execute when needed. It should also be noted that each process is executed once upon powering up the system. A wait statement is similar to the sensitivity list with a couple of extra advantages. A wait statement can be placed anywhere withing the body of a process, and there is no limit to the number of wait statements that can be used within one process. A wait statement can wait on a specific signal, length of time or a Boolean expression.

19. 19 Process syntax of a counter count: process (x) variable cnt : integer := -1; begin cnt:=cnt + 1; end process This is the basic syntax for a process statement. The process label, although optional, is strongly suggested since it aids in finding errors when debugging your code. Between the process and the begin statement is where the variables are declared. Since the process is executed once upon startup, this variable is initialized to -1 so that it can accurately count the number of times signal x changes.This is the basic syntax for a process statement. The process label, although optional, is strongly suggested since it aids in finding errors when debugging your code. Between the process and the begin statement is where the variables are declared. Since the process is executed once upon startup, this variable is initialized to -1 so that it can accurately count the number of times signal x changes.

20. 20 Variables Variables in VHDL behave similar to those in conventional programming languages They are used to represent the state of a process and are local to that process They are declared in a similar way to that of a signal in data flow or structural descriptions variable TempVar : integer := -1; As shown above, Variables are declared before the begin keyword of a process Variables in VHDL are similar to those in conventional programming languages, but are local to only that specific process. They represent the state in which the process is currently in, holding their values until the next time the process is executed. Variables are declared the same way as signals, between the process statement and the begin statement.Variables in VHDL are similar to those in conventional programming languages, but are local to only that specific process. They represent the state in which the process is currently in, holding their values until the next time the process is executed. Variables are declared the same way as signals, between the process statement and the begin statement.

21. 21 Variables and signals signal x, y, z : bit; process (y) begin x<=y; z<=not x; end process It should be noted that signals and variables are quite different. Signal assignment statements do not take effect immediately. They can also be overwritten, where variables take effect immediately. On the left both commands in the process are concurrent, they occur at the same time. This results in Z not being the opposite of Y but actually Z is the opposite of the previous value of X Since the example on the right is using variables, which are sequential in nature, the value of z is indeed the complement of Y. It should be noted that signals and variables are quite different. Signal assignment statements do not take effect immediately. They can also be overwritten, where variables take effect immediately. On the left both commands in the process are concurrent, they occur at the same time. This results in Z not being the opposite of Y but actually Z is the opposite of the previous value of X Since the example on the right is using variables, which are sequential in nature, the value of z is indeed the complement of Y.

22. 22 Behavioral vs. Structural vs. Data flow In summery, Structural descriptions is a way of combining multiple components to create a circuit. Data flow is a way of describing the actual flow of signals from the input to the output Behavioral is a way of using sequential commands within a process to describe the behavior of the circuitIn summery, Structural descriptions is a way of combining multiple components to create a circuit. Data flow is a way of describing the actual flow of signals from the input to the output Behavioral is a way of using sequential commands within a process to describe the behavior of the circuit

23. 23 Files and Input/Output A method of viewing and storing the results produced by simulation They are used for long term data storage beyond just one simulation run Saving result data to be analyzed in other programs Assists in error checking your circuit File handling can only be done during simulation of a circuit. In VHDL, a file can only contain one type of object (bit, integer, bit_vector, text, etc) The concept behind file handling in VHDL is similar to that of conventional programming languages except that you must declare a file object type. Declaring a file pointer of specified object type Opening the file Reading/Writing data File operations are a useful way of viewing data generated during a simulation. They can also be used for storing data values so that they may be utilized in simulations. It is also useful for generating data to be plotted using spreadsheets as well as error checkingFile operations are a useful way of viewing data generated during a simulation. They can also be used for storing data values so that they may be utilized in simulations. It is also useful for generating data to be plotted using spreadsheets as well as error checking

24. 24 Definition of File Type The first step is to define the type of file in use, the type of information stored in that file type. type file_type is file of element_type; type IntegerFileType is file of integer; which defines IntegerFileType as a type that can only contain integer values Once you have defined the type of file in use, the next step is the file declaration. A file declaration creates one or more file objects (pointers) of a given file type. File declarations occur between the process statement and the begin statement (similar to variables) There are different declarations depending on the version of VHDL being used. The first step is to define the type data that the file will be. This means that this file can only hold this type of data. Once the file type is determined the next step is to declare the file pointers.The first step is to define the type data that the file will be. This means that this file can only hold this type of data. Once the file type is determined the next step is to declare the file pointers.

25. 25 File Declaration The syntax for VHDL-93 is followed: file identifier (,�) : subtype_indication [open file_open_kind is �filename� ]; file_open_kind: read_mode write_mode append_mode Example: file infile: IntegerFileType open read_mode is �inputdata.txt� file outfile: IntegerFileType open write_mode is �outputdata.txt�; The syntax for VHDL-87 is followed: file identifier : subtype_indication is [in | out] string_expression ; Example: file infile: IntegerFileType is in �inputdata.txt�; file outfile: IntegerFileType is out �outputdata.txt�; How the files are declared is dependent on the version of VHDL used. Each of these declarations are done before the begin statement in a process How the files are declared is dependent on the version of VHDL used. Each of these declarations are done before the begin statement in a process

26. 26 file_open / file_close Another way of opening files in VHDL-93 is similar to the conventional C programming language the object of the file is created but the file is opened and closed within the body of the code file_open and file_close commands are used to open and close the files. In VHDL 93, there is another way of declaring and opening files. This is using File_open and File_close. This technique allows the system to declare the pointer, without actually opening the file. Unlike the previous method, this method of opening and closing can be done in the body of the process. . In VHDL 93, there is another way of declaring and opening files. This is using File_open and File_close. This technique allows the system to declare the pointer, without actually opening the file. Unlike the previous method, this method of opening and closing can be done in the body of the process. .

27. 27 Advantage of file_open/file_close Determine how to open the file within program (read, write, append) Can determine the name of the file you wish to open during the program (ie. User type in keyboard) Allows the system to ensure the file is opened properly file_open_status is used to verify the open operation is successfully. Problems can occur if the file is declared in a component that is used multiple times. Each instant of the component will attempt to open the same file There are a couple of advantages to this method of opening a file. These include allowing the program to determine how the file should be opened, which mode. Allows the name of the file to be also dynamic. One of the most important advantages is the file open status. This is ude to verify that the file is opened successfully. A common problem that might arise is that if the file is declared within a componenent and that component is used multiple times, then the simulation would attempt to access this file multiple times.There are a couple of advantages to this method of opening a file. These include allowing the program to determine how the file should be opened, which mode. Allows the name of the file to be also dynamic. One of the most important advantages is the file open status. This is ude to verify that the file is opened successfully. A common problem that might arise is that if the file is declared within a componenent and that component is used multiple times, then the simulation would attempt to access this file multiple times.

28. 28 File Reading and Writing In the basic reading and writing, the data stored and retrieved must be of the same type as the file declaration In order to read from a file, the file must be opened in read_mode. In writing information to a file, the file must be opened in either write_mode or append_mode. This method of reading and writing is not very popular since it is bad for portability between operating systems and simulators. As mentioned before, when using the basic reading and writing commands, the values that are put in them can only be of one type. Also, there might be a portability issue between different operating systems and simulators. As mentioned before, when using the basic reading and writing commands, the values that are put in them can only be of one type. Also, there might be a portability issue between different operating systems and simulators.

29. 29 Textio Package Textio is a standardized library for VHDL that allows data to be stored to a monitor or to a file in ASCII format The standard library must be included at the top of the code use std.textio.all; This increases the portability the data that is being stored so that it may be used on other simulators or platforms It allows external software to read results for analyzing (spreadsheet, human eye, etc). When defining a file for reading and writing using the Textio functions, the file declaration is of file type text It is based on the concept of dynamic strings, accessed using pointers of type line Textio uses the same idea as normal read/write to write the line of text to a file, but uses a command called writeline. The difference is when creating the string of text, it converts all data to text Textio is a standard library that comes with all VHDL packages. It is used to convert data that wishes to be stored to a file into text. To use this library, std.textio.all; must be included at the top of the code. There are several reasons for the textio package. First, it increases the portability of the data. This allows the data to be used on different operating systems and well as it allows different simulators to use the data. It allows the data to be in a format that can be imported into spread sheets and understood by the human eye. This makes it good for understanding the actual operation of the system. Textio formats its data in a different way then the other read and write techniques. In this technique, all the data is formatted into a line of text. Once all the data is placed into the line, it is written to the file. The read operation is the opposite. It reads a entire line, then extracts the data one by one.Textio is a standard library that comes with all VHDL packages. It is used to convert data that wishes to be stored to a file into text. To use this library, std.textio.all; must be included at the top of the code. There are several reasons for the textio package. First, it increases the portability of the data. This allows the data to be used on different operating systems and well as it allows different simulators to use the data. It allows the data to be in a format that can be imported into spread sheets and understood by the human eye. This makes it good for understanding the actual operation of the system. Textio formats its data in a different way then the other read and write techniques. In this technique, all the data is formatted into a line of text. Once all the data is placed into the line, it is written to the file. The read operation is the opposite. It reads a entire line, then extracts the data one by one.

30. 30 Writing information using Textio In order to write information using Textio, the information must be formatted in a variable Because of the variables, this operation must occur in a process A write function converts the data to text and appends it to the end of the variable This data can be bit, bit_vector, time, integer, real, boolean, character and string Writeline is used to write the information in the variable to the file, then resetting the variable to null. To write information into the line of text uses the same commands as writing data to a file in the other technique. The only difference is that instead of using the file pointer as the first argument, the buffer of text is used. Once all the data is placed into the text buffer the information is written to the file.To write information into the line of text uses the same commands as writing data to a file in the other technique. The only difference is that instead of using the file pointer as the first argument, the buffer of text is used. Once all the data is placed into the text buffer the information is written to the file.

31. 31 Example of Writing to file use textio.all; architecture behavior of check is begin process (x) variable s : line variable cnt : integer := 0; file output : TEXT is out �data.txt"; begin if (x = �1� and x�last_value = �0�) then cnt:=cnt+1; if (cnt>MAX_COUNT) then write (s, �Overflow � �); write (s, cnt); writeline (output, s); end if; end if; end process; end behavior

32. 32 Reading information using Textio The reading of data is similar to the writing of data The readline reads a complete line of data from the file and places it in a pointer of type line The read function extracts characters from the beginning of the line and converts them into the expected type In reading a string or a bit_vector of a certain length, it converts as much information as will fit into the variable There is a optional parameter in the read command called good Good is a Boolean value that returns if the read is successful or unsccessful depending on if there is a problem reading the data As mentioned above, the input from textio is the opposite to the writing of data. A full line of data is read into a buffer, then each value is extracted from that line using the read command.As mentioned above, the input from textio is the opposite to the writing of data. A full line of data is read into a buffer, then each value is extracted from that line using the read command.

33. 33 Textio Input Example procedure read_v1d(variable v:out std_logic_vector) is variable buf : line; variable c : character ; file out_file : TEXT is in �data.txt"; begin readline (f , buf ); --read a line from the file. for i in v �range loop read( buf , c ) ; --read a character from the line. case c is when �X� => v (i) := �X� ; when �U� => v (i) := �U� ; when �Z� => v (i) := �Z� ; when �0� => v (i) := �0� ; when �1� => v (i) := �1� ; when �-� => v (i) := �-� ; when �W� => v (i) := �W� ; when �L� => v (i) := �L� ; when �H� => v (i) := �H� ; when others => v (i) := �0 �; end case; end loop; end;

34. 34 File Declared in subprograms If a file object is declared in an architecture or a process, the files are opened at the start of the simulation and automatically closed again at the end of the simulation. Opening files in a subprogram are local to only that subprogram and are automatically closed once the subprogram returns Each time the procedure is called, a new physical file is created. Example procedure write_to_file is file FilePtr : data_file_type open write_mode is �datafile�; begin � end procedure write_to_file; A subprogram (which guangfa will discuss later) is similar to functions in C. A new file is created each time a subprogram is executed and these files are local to the subprogram. When the subprogram is finishes executing, the file is closed on returning.A subprogram (which guangfa will discuss later) is similar to functions in C. A new file is created each time a subprogram is executed and these files are local to the subprogram. When the subprogram is finishes executing, the file is closed on returning.

35. 35 VHDL Test Bench VHDL test bench is VHDL code that produces stimuli to test your design correctness It can automatically verify accuracy of the VHDL code Given a known input, does the system generate the expected output Verifies that the VHDL code meets the circuits specifications Test benches should be easily modified, allowing for future use with other code Should be Easy to understand the behavior of the test bench

36. 36 Purpose for Test Bench To generate stimulus signals for simulation Generate specific stimuli based on the previous output response Apply a basic waveform with discrete time intervals Import test data from files b) To apply these stimulus to the VHDL code under test and collect the actual output responses c) To compare the output responses with the values expected

37. 37 Stimulus Generation/Response There is three general ways of generating a simulation for testing Repetitive patterns Patterns can generated using different frequencies and periods Combination of waveforms (Waveform A and B) Lookup table Constant table I/O data Keyboard Data file Response Handling The response from the system can be dumped to a file to be analyzed by a external program or human eye (Textio). Analyzed by test bench to verify expected output.

38. 38 Test Bench

39. 39 Full Adder Sample Test Bench with output ARCHITECTURE testbench_arch OF testbench IS COMPONENT full_adder PORT (a, b, c : in� std_logic;sum, carry : out� std_logic); END COMPONENT; SIGNAL a , b, c, sum, carry : std_logic; --Defining the variable "CLK_PERIOD" --to be equal to 20 nano seconds constant CLK_PERIOD : time:= 20 ns; BEGIN--Defining external interface signals --to Unit Under Test.� UUT : full_adder PORT MAP ( a => a, b => b, c => c, sum => sum, carry => carry); CLOCK: process�� begin��� a <= '0';���� wait for CLK_PERIOD/2;���� a <= '1';���� wait for CLK_PERIOD/2; end process;

40. 40 Full Adder Sample Test Bench with output 2 ARCHITECTURE testbench_arch OF testbench IS COMPONENT full_adder PORT (a, b, c : in� std_logic;sum, carry : out� std_logic); END COMPONENT; SIGNAL a , b, c, sum, carry : std_logic; --Defining the variable "CLK_PERIOD" --to be equal to 20 nano seconds constant CLK_PERIOD : time:= 20 ns; BEGIN--Defining external interface signals --to Unit Under Test.� UUT : full_adder PORT MAP ( a => a, b => b, c => c, sum => sum, carry => carry); READDATA: process file out_file : TEXT is in �data.txt"; variable buf : line; variable A,B,C : std_logic ; begin readline (f , buf ); --read a line from the file. read( buf , A ) ; --read a character from the line. read( buf , B ) ; read( buf , C ) ; a<=A; b<=B; c<=C; wait for CLK_PERIOD; end process