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HAZARDS - Data hazards are performance issues in pipelined processors that occur when an instruction depends on the result of a previous instruction that has not yet completed. This can lead to incorrect results or pipeline stalls, requiring solutions like data forwarding or stalling the pipeline. The three main types are Read After Write (RAW), Write After Read (WAR), and Write After Write (WAW). <br>Types of data hazards<br>Read After Write (RAW): Also known as a "true dependency," this is the most common type. It occurs when an instruction needs the result of a previous instruction that it has n
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SNS COLLEGE OF TECHNOLOGYAn Autonomous Institution Coimbatore-35 • 23ITT202 – Computer Organization • & • Architecture • IIB.E CSE/ III SEMESTER Department of Computer Science & Engineering UNIT III : Processor & Pipelining Topic 3 : Pipelining & Hazards
Let’s Recall !! Why pipeline Pipeline performance Definition Types Advantages Drawbacks COA\Processor & Pipelining \ K.Sangeetha \ SNSCT
Topics for discussion • Hazards • Types of Hazards COA\Processor & Pipelining \ K.Sangeetha \ SNSCT
BrainStorm!! COA\Processor & Pipelining \ K.Sangeetha \ SNSCT
Hazard COA\Processor & Pipelining \ K.Sangeetha \ SNSCT
Conventional • Execution of Three Instructions in a 4-Stage Pipeline
Pipeline Performance • The potential increase in performance resulting from pipelining is proportional to the number of pipeline stages. • However, this increase would be achieved only if all pipeline stages require the same time to complete, and there is no interruption throughout program execution. • Unfortunately, this is not true. • Floating point may involve many clock cycle • Stalling involves halting the flow of instructions until the required result is ready to be used. However stalling wastes processor time by doing nothing while waiting for the result. • Pipeline stall causes degradation in pipeline performance.
Pipeline Performance • Any condition that causes a pipeline to stall is called a hazard. Data hazard – when an instruction depend on the result of a previous instruction, but this result is not yet available. • Instruction (control) hazard – a delay in the availability of an instruction causes the pipeline to stall for example branch. • Structural hazard – the situation when two instructions require the use of a given hardware resource at the same time.
Data Hazards • We must ensure that the results obtained when instructions are executed in a pipelined processor are identical to those obtained when the same instructions are executed sequentially. • Hazard occurs A ← 3 + A B ← 4 × A • No hazard A ← 5 × C B ← 20 + C • When two operations depend on each other, they must be executed sequentially in the correct order. • Another example: Mul R2, R3, R4 Add R5, R4, R6
Pipeline stalled by data dependency between D2 and W1. Data Hazards Mul R2, R3, R4 Add R5, R4, R6
Data dependency solutions • Hardware interlocks: is a circuit that detects instructions whose source operands are destinations of instructions Farther up in the pipeline. • Operand forwarding : uses special h/w to detect a conflict and then avoid it by routing the data through special paths between pipeline segments . • delayed load :the compiler for such computers is designed to detect a data conflict and reorder the instructions as necessary to delay the loading of the Conflicting data by inserting no –operation instructions. Example I1: Mul R2, R3, R4 NOP NOP I2: Add R5, R4, R6
Instruction Hazards • One of the major problems in operating an instruction pipeline is the occurrence of branch instructions. • 1- Unconditional branch always change the sequential program flow by loading the program counter with the target address. • 2- Conditional branch the control selects the target instruction if the condition is satisfied or the next sequential instruction if the condition is not satisfied.
Unconditional Branches • The time lost as a result of a branch instruction is referred to as the branch penalty. • The previous example instruction I3 is wrongly fetched and branch target address k will discard the i3. • Typically the Fetch unit has dedicated h/w which will identify the branch target address as quick as possible after an instruction is fetched.
Instruction Queue and Prefetching • branch instruction stalls the pipeline. • Many processor employs dedicated fetch unit which will fetch the instruction and put them into a queue. • It can store several instruction at a time. • A separate unit called dispatch unit, takes instructions from the front of the queue and send them to the execution unit.
Instruction Queue and Prefetching Instruction fetch unit Instruction queue F : Fetch instruction D : Dispatch/ E : Ex ecute W : Write Decode instruction results unit Use of an instruction queue in the hardware organization of Figure 8.2b.
2- Conditional Branches • A conditional branch instruction introduces the added hazard caused by the dependency of the branch condition on the result of a previous instruction. • The decision to branch cannot be made until the execution of that instruction has been completed.
Delayed Branch LOOP Shift_left R1 Decrement R2 Branch=0 LOOP NEXT Add R1,R3 (a) Original program loop LOOP Decrement R2 Branch=0 LOOP Shift_left R1 NEXT Add R1,R3 (b) Reordered instructions Reordering of instructions for a delayed branch.
References • Carl Hamacher, ZvonkoVranesic and SafwatZaky,“Computer Organization”, McGraw-Hill,5th Edition 2014. 09-10-2025 COA\Processor & Pipelining \ K.Sangeetha \ SNSCT
