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Chapter 2: Computer Systems Organization CS 271 Computer Architecture Indiana University – Purdue University Fort Wayne Mark Temte Review of computer organization Processors Primary memory Secondary memory Input / Output Processor topics Basic bus-oriented computer CPU organization

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chapter 2 computer systems organization

Chapter 2: Computer Systems Organization

CS 271 Computer Architecture

Indiana University – Purdue University Fort Wayne

Mark Temte

review of computer organization
Review of computer organization
  • Processors
  • Primary memory
  • Secondary memory
  • Input / Output
processor topics
Processor topics
  • Basic bus-oriented computer
  • CPU organization
  • Fetch-execute cycle
  • RISC
  • Instruction-level parallelism
  • Processor-level parallelism
basic bus oriented computer
Basic bus-oriented computer

The bus, physically, is just parallel wires

It is controlled by a bus arbiter device

cpu organization
CPU organization
  • Data path
    • Part of the CPU
    • Registers
    • ALU
    • Internal buses
    • Data path cycle
  • ALU
    • +, -, /, *
    • AND, OR, NOT
  • Registers
    • PC, IR, MAR, MBR
    • General purpose
    • Special purpose
fetch execute cycle
Fetch-execute cycle

1. Fetch the next instruction from the memory location referred to by the PC register and place it in the IR

2. Increment the PC

3. Decode the instruction in the IR register

4. Calculate any memory operand address and place it in the MAR register

5. Fetch any operand from memory and place in the MBR register

6. Execute the instruction

7. Repeat until the HALT instruction is executed

risc vrs cisc
RISC vrs. CISC
  • RISC (Reduced Instruction Set Computer)
  • CISC (Complex Instruction Set Computer)
  • Microarchitecture interpretation (CISC) dominated until the 1980s
  • VAX computer system
    • Epitome of CISC
    • Very high-level ISA instruction set
  • RISC is favored by faster memory and cache technology
risc design principles
RISC design principles
  • Avoid microinterpretion
  • Use pipelining to increase throughput
    • This may require out-of-order execution
  • Make instructions simple
    • Few formats
    • Fixed lengths
    • Few operands
  • Only LOAD and STORE instructions should reference memory
  • Have many registers
instruction level parallelism
Instruction-level parallelism
  • Pipelining
  • Superscalar architecture
pipelining
Pipelining
  • Production line with “stages”
  • Latency
    • Time to execute one instruction
  • Processor bandwidth
    • The number of MIPS (Millions of Instructions Per Second)
  • Note that the results from one instruction may be needed by the next instruction
pipelining11
Pipelining

A five-stage pipeline

superscalar architecture
Superscalar architecture
  • Pipeline bottleneck is the execute stage
  • Introduce multiple functional units for this stage
processor level parallelism
Processor-level parallelism
  • Array and vector computers
    • SIMD
  • Multiprocessor
    • MIMD
    • Many CPUs
    • Shared memory
  • Multicomputer
    • MIMD
    • Each has its own . . .
      • CPU
      • Local memory
primary memory
Primary memory
  • Cell
    • Smallest addressable unit
  • k-bit cell
    • 2k different bit combinations
  • Usually . . .
    • k = 8
    • Cell = 1 byte
primary memory16
Primary memory
  • Word
    • Group of cells acted upon as a unit
    • 32-bit word (= 4 bytes) is typical
    • 64-bit words are available
      • Intel Itanium processor
      • IBM and Apple PowerPC G5 processor
    • Register size defines the word size
primary memory17
Primary memory

Bytes within words might be arranged in “big endian” order or in “little endian” order

cache memory
Cache memory
  • Just one CPU cycle per memory cycle would slow the CPU considerably
  • So, keep heavily used cells in a special fast “cache” memory
  • Before fetching a cell from memory, check if it is in the cache
cache memory19
Cache memory
  • Cache miss?
    • Bring in an entire “cache line”
    • Cache line is typically 64 contiguous bytes
  • Principle of locality
    • Memory references made during a short period of time tend to cluster around a few memory locations
    • Consider . . .
      • a tight loop in a program
      • local variables in a method
multilevel cache memory
Multilevel cache memory

CPU

cache

tertiary cache

primary memory

secondary

cache

memory packaging
Memory packaging
  • SIMM (Single Inline Memory Module)
  • A group of chips (typically 8 or 16) is mounted on a circuit board with connectors
primary secondary memory hierarchy
Primary / secondary memory hierarchy

faster – more expensive – smaller capacity

slower – cheaper – larger capacity

winchester disk
Winchester disk
  • Sealed “hard” disk
  • Rotation speed typically 7200 rpm
  • About 5000 to 10,000 concentric tracks per cm
  • About 100,000 bits per cm around circumference

sectors

read-write head

track

winchester disk multiplatter configuration26
Winchester disk - multiplatter configuration

All the tracks at a given radial distance are called a cylinder

boom

cylinder

winchester disk speed
Winchester disk speed
  • Seek time
    • Time for the head to move to desired track
    • About 5 – 10 msec
  • Latency time
    • Time for the disk to spin around to the desired sector
    • About 4 msec at 7200 rpm
  • Transfer time
    • Time to read or write a sector
    • Less than 0.1 msec
floppy disk
Floppy disk
  • IDE
    • Integrated Drive Electronics
    • Controller on drive unit
    • Low cost
  • SCSI
    • Small Computer System Interface
    • Pronounced “scuzzy”
    • Fast, high end
    • Possible to daisy-chain SCSI devices
slide29
RAID
  • Redundant Array of Inexpensive Disks
  • Allows parallel access to separate disks
  • Provides for data redundancy
  • 6 levels
    • 0 – no redundancy
    • 1 – each disk has backup
      • Reading is from the quickest disk
      • Writing must be done to both disks
    • 2 & 3 – one bit of data per disk
      • High throughput
      • Error correction
  • Strip = string of sectors
cd rom32
CD-ROM
  • Constant streaming rate
    • 120 cm per sec (single speed)
    • Rotation rate not constant
      • 530 – 200 rpm
  • Symbol
    • Represents 1 byte
    • Requires 14 bits
  • Error correction included
    • Uses the extra 6 bits
cd rom33
CD-ROM
  • Symbols are organized into frames and frames into sectors
  • Frame
    • Uses 42 symbols
    • Represents only 24 bytes of data
  • Sector
    • 98 frames
    • Represents only 2048 bytes of data
cd rom35
CD-ROM
  • Capacity
    • About 650 MB
  • Access rate (32X)
    • Less than 5 MB per second
  • Seek time
    • Greater than 100 msec
  • Varieties: CD-R, CD-RW, DVD, Blu-Ray, etc.
input output
Input / Output
  • I/O devices connect indirectly to the system bus
  • System bus is located on the motherboard
  • Motherboard contains . . .
    • CPU
    • SIMM sockets
    • Other chips
    • System bus with sockets for edge connectors of boards
  • Board
    • Usually the controller of a device
  • Device
    • Typically connected to board by a ribbon cable
system bus
System bus
  • Bus arbiter
    • Chip on motherboard
    • Grants access to the system bus
    • Device controllers compete with the CPU for bus access
    • Preference goes to devices over the CPU
      • This is called “cycle stealing”
system bus39
System bus
  • Example - DMA (Direct Memory Access)
    • Disk controller transfers a block of data between memory and disk without CPU intervention
    • Competes with the CPU for bus (and memory) access
    • Sends interrupt to the CPU when done
    • In response, the CPU runs an interrupt handler to update operating system records
typical system buses
Typical system buses
  • Original IBM PC bus
    • 62 lines
    • 8 bits per transfer
  • ISA (Industry Standard Architecture) bus
    • Bus for the IBM PC/AT (Intel 286)
    • 98 lines
  • EISA bus
    • ISA with more lines for 32-bit transfers
  • PCI bus
    • Peripheral Component Interconnect
  • USB
    • Universal Serial Bus
i o devices42
I/O Devices
  • Keyboard
    • Interrupt generated whenever key is pressed or released
  • Mouse
    • Sends 3 bytes whenever it moves
      • Change in x
      • Change in y
      • Button state
i o devices43
I/O Devices
  • Monitor
    • CRT and flat panel
    • Terminals are character map or video map
    • Character map terminal
      • Renders characters on the screen
      • Holds lines of character codes
      • 25 lines x 80 characters per line = 2000 codes
      • Plus 2000 attributes
      • So, a character map video memory requires 4000 bytes
i o devices44
I/O Devices
  • Monitor (continued)
    • Bit map terminal
      • VGA (early standard)
        • 640pixels x 480 pixels = 307,200 pixels
      • Software renders characters in pixels
      • Color uses 8, 16, 24, or 32 bits per pixel
      • Video ram memory
        • Holds the bit map
        • 5.5 MB for 1600 x 1200 @ 3 bytes / pixel
    • Video display
      • Requires huge bandwidth – 137.5 MB/sec
      • AGP (Accelerated Graphics Port) bus
i o devices45
I/O Devices
  • Printer
    • Dot matrix
      • Old technology
    • Inkjet
    • Laser
    • Gray scale
      • Implemented with halftone technique
    • Color
      • Printed with cyan, yellow, magenta, and black ink (CYMK)
      • Monitors use RGB instead
telecommunications
Telecommunications
  • RS-232-C interface
    • RS-232-C is a standard computer-terminal interface
    • It is a protocol and specification for sending signals
    • When a telephone line is used to connect a computer and a terminal, two modems are needed . . .
      • Between the computer and telephone line
      • Between the telephone line and terminal
telecommunications47
Telecommunications
  • Modem
    • MOdulator – DEModulator
    • For communication over telephone lines
    • Uses a UART chip
      • Universal Asynchronous Receiver Transmitter
      • Converts parallel (byte stream) to serial (bits stream) and back
    • Analog telephone signal is modulated
      • Amplitude
      • Frequency
      • Phase
    • Supports full-duplex
      • Simultaneous transmission in both directions
various modulation techniques
Various modulation techniques

Modulation by: (a) Two-level signal (b) Amplitude modulation (c) Frequency modulation and (d) Phase modulation