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An NLTL based Integrated Circuit for a 70-200 GHz VNA System

An NLTL based Integrated Circuit for a 70-200 GHz VNA System

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An NLTL based Integrated Circuit for a 70-200 GHz VNA System

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  1. An NLTL based Integrated Circuit for a 70-200 GHz VNA System O. Wohlgemuth, B.Agarwal*, R. Pullela*, D. Mensa*, Q. Lee*, J. Guthrie*, M. J. W. Rodwell*, R. Reuter, J. Braunstein, M. Schlechtweg, T. Krems, K. Köhler Fraunhofer Institute for Applied Solid State Physics (IAF),Tullastr. 72, D-79108 Freiburg - Germany *Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106 Archivierungsangabe

  2. Outline • Motivation • Conventional S-parameter measurement set-up and integration on a chip • Design and fabrication • Performance of the • integrated components • full chip • Summary Archivierungsangabe

  3. Advancement in III-V technology especially in InP based devices HEMTs and HBTs with fmax > 500 GHz ICs, operating above 120 GHz Presently no commercial broadband on-wafer S-parameter measurement system above 120 GHz available Motivation Archivierungsangabe

  4. Measurement System Archivierungsangabe

  5. Block Diagram of the Chip Archivierungsangabe

  6. NLTL • Limiting faktors: • Bragg Frequency • Skin-effect loss and diode loss MD, 26th EuMC 1996

  7. Technology • Planar Schottky diode process • N- layer exponential doped • Further process steps: • Interconnect metal, • Si3N4 • Air bridges MD, 26th EuMC 1996

  8. Problems with High Drive Frequency • High skin-effect losses • DC walk of because of the high loss • Doides are driven through a minor capacitance variation • Only low power available • Long lines neccassary, to reach enough compression MD, 26th EuMC 1996

  9. Design of the Multiplier NLTL • Bragg frequency increases exponential • Air bridge line combines wide center conductor with high Bragg frequency Line length: 4.2 mm MD, 26th EuMC 1996

  10. Waveform at the Output of the Multiplier NLTL • Input: • 36 GHz sine wave with 12 dBm power • Measured output: • ~4.1 ps fall time Archivierungsangabe

  11. Coupler designed for 10 dB coupling Zeven, Zodd, geven and godd are calculated with a 3D simulator (HFSS) Measured directivity of the coupler using on-wafer sampling circuits Directional Coupler Designed for 180 GHz MD, 26th EuMC 1996

  12. Low Pass Filter Low pass filter neccassary with low reflection over the entire bandwidth ZL=75W C choosen for Zeff=50W MD, 26th EuMC 1996

  13. Nonlinearity of the Sampling Circuits • Sampling circuit was driven with a input frequency of 36 GHz • Harmonic generation is negligible for input powers below 0 dBm MD, 26th EuMC 1996

  14. Not in the simulation included are: Attenuation of the sampling circuit Skin-effect losses of the coupler -35 dBm @ 200 GHz is sufficient for measuring Power at the DUT Archivierungsangabe

  15. Measurement of 2 Chips 50 W (44 +/-1.5 W) chip resistor open test port Measured Directivity of the Full Chip MD, 26th EuMC 1996

  16. Summary • The first IC, which can be used as a S-parameter test set within 70-200 GHz • Design and fabrication • Performance of the single components and the full chip • Packaging these chips into active probes will permit convenient on-wafer S-parameter measurements This work was supported by the German Ministry BMBF in the frame work of 01BM620 (555339) Archivierungsangabe