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CSCE-212-Intro-To-Computer-Architecture-Lecture7-MicroArchitecture

CSCE-212-Introduction to Computer Architecture-Lecture-7-Fall 2024-Mehdi Yaghouti

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CSCE-212-Intro-To-Computer-Architecture-Lecture7-MicroArchitecture

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  1. Microarchitecture University of South Carolina Introduction to Computer Architecture Fall, 2024 Instructor: Mehdi Yaghouti MehdiYaghouti@gmail.com Introduction to Computer Architecture, 2024 1/79 University of South Carolina (M. Y.) USC

  2. Microarchitecture A computer architecture is defined by its instruction set and architectural state RISC-V architectural state: the program counter and the 32 X 32-bit registers Architectural state and memory hold all the needed information to resume Microarchitecture is the connection between logic and architecture Microarchitecture is the arrangement of: Registers Arithmetic Logic Units (ALUs) Finite State Machines (FSMs) Memories Logic building blocks needed to implement a specific architecture Microarchitecture can be considered to be composed of datapath and control unit datapath is the path in which the data flow between different components control unit controls the datapath based on the current instruction at hand Introduction to Computer Architecture, 2024 2/79 University of South Carolina (M. Y.) USC

  3. Main Components Program counter (PC) points to the current instruction PCNext, indicates the address of the next instruction Instruction memory takes a 32-bit address A and reads the data Register file has two read ports and one write port Read ports take 5-bit address inputs, A1 and A2 Register file places the 32-bit register values onto RD1 and RD2 It takes a 5-bit address input A3 and a 32-bit write data WD3 If WE3 is asserted, the data WD3 will be written into address A3 Writing happens at the clock edge Data memory has a single read/write port It reads data at address A and places it into RD If WE is asserted it writes WD into address A at the clock edge Introduction to Computer Architecture, 2024 3/79 University of South Carolina (M. Y.) USC

  4. Microarchitecture (Single Cycle CPU) Fetch PC is the current instruction address Each word is 32 bits PCNext ← PC + 4 PC only changes at the clock transition Branch instructions need to set the PCNext Introduction to Computer Architecture, 2024 4/79 University of South Carolina (M. Y.) USC

  5. Microarchitecture (Single Cycle CPU) Bitfield Extraction PC is the current instruction address Introduction to Computer Architecture, 2024 5/79 University of South Carolina (M. Y.) USC

  6. Microarchitecture (Single Cycle CPU) Registers PC is the current instruction address Introduction to Computer Architecture, 2024 6/79 University of South Carolina (M. Y.) USC

  7. Microarchitecture (Single Cycle CPU) Extension Unit PC is the current instruction address Introduction to Computer Architecture, 2024 7/79 University of South Carolina (M. Y.) USC

  8. Microarchitecture (Single Cycle CPU) Sign Extension PC is the current instruction address Introduction to Computer Architecture, 2024 8/79 University of South Carolina (M. Y.) USC

  9. Microarchitecture (Single Cycle CPU) ALU PC is the current instruction address Introduction to Computer Architecture, 2024 9/79 University of South Carolina (M. Y.) USC

  10. Microarchitecture (Single Cycle CPU) Load Instruction lw rd, imm(rs1) 1 Read one source register 2 Perform addition with immediate 3 Write the second source register into data memory Introduction to Computer Architecture, 2024 10/79 University of South Carolina (M. Y.) USC

  11. Microarchitecture (Single Cycle CPU) Store Instruction sw rs2, imm(rs1) 1 Read two source registers 2 Perform addition between a source register and immediate 3 Write the second source register into the memory Introduction to Computer Architecture, 2024 11/79 University of South Carolina (M. Y.) USC

  12. Microarchitecture (Single Cycle CPU) R-Type Instruction add, sub, and, or, slt They only differ in ALUControl add rd, rs1, rs2, 1 Read two source registers 2 Perform ALU operation 3 Write back the ALU result into destination register Introduction to Computer Architecture, 2024 12/79 University of South Carolina (M. Y.) USC

  13. Microarchitecture (Single Cycle CPU) I-Type Instruction addi, andi, ori, slti They only differ in ALUControl addi rd, rs1, imm, 1 Read one source register 2 Perform ALU operation between the source and Imm 3 Write back the ALU result into destination register Introduction to Computer Architecture, 2024 13/79 University of South Carolina (M. Y.) USC

  14. Microarchitecture (Single Cycle CPU) Conditional Branch beq rs1, rs2, addr, 1 Read two source registers 2 Perform the subtraction and issue Z 3 Calculate PC+Imm 4 Choose the select signal for PCSrc Introduction to Computer Architecture, 2024 14/79 University of South Carolina (M. Y.) USC

  15. Microarchitecture (Single Cycle CPU) Jump Instruction jal rd, label, 1 Jump to Pc+imm 2 Write Pc+4 into rd Introduction to Computer Architecture, 2024 15/79 University of South Carolina (M. Y.) USC

  16. Microarchitecture (Single Cycle CPU) Control Unit Op (6:0), func3 (14:12) and func7 (30) are the inputs to the control unit Outputs: PCSrc,ImmSrc,RegWrite,ALUSrc,ALUControl,MemWrite,ResultSrc Introduction to Computer Architecture, 2024 16/79 University of South Carolina (M. Y.) USC

  17. Microarchitecture (Single Cycle CPU) Control Unit Main Decoder truth tabel Introduction to Computer Architecture, 2024 17/79 University of South Carolina (M. Y.) USC

  18. Microarchitecture (Single Cycle CPU) Control Unit ALU truth tabel Introduction to Computer Architecture, 2024 18/79 University of South Carolina (M. Y.) USC

  19. Microarchitecture (Single Cycle CPU) Performance Analysis The CPU performance 1 ExecutionTime = (#Inst.) × (CPI) × In single cycle CPU, CPI=1 The cycle time is set by the critical path lw has the longest path Fclock Tsingle= tpcq+tmem+max{tRFread,tdec+text+tmux}+tALU+tmem+tmux+tRFsetup Assuming that tRFread> tdec+ text+ tmux, Tsingle= tpcq+ 2tmem+ tRFread+ tALU + tmux+ tRFsetup Introduction to Computer Architecture, 2024 19/79 University of South Carolina (M. Y.) USC

  20. Microarchitecture (Single Cycle CPU) Performance Analysis Using the following table, the clock cycle can be estimated as Tsingle= tpcq+ 2tmem+ tRFread+ tALU + tmux+ tRFsetup = 40 + 2 × 200 + 100 + 120 + 30 + 60 = 750ps Introduction to Computer Architecture, 2024 20/79 University of South Carolina (M. Y.) USC

  21. Microarchitecture (Single Cycle CPU) Disadvantages Requires a clock cycle long enough to support the slowest instruction Requires separate memories for instructions and data Hardware are not being used efficiently, e.g. one adder for each task Introduction to Computer Architecture, 2024 21/79 University of South Carolina (M. Y.) USC

  22. Microarchitecture (Multi Cycle CPU) Combining the Memories Instruction and Data memories can be unified using a multiplexer for the address Introduction to Computer Architecture, 2024 22/79 University of South Carolina (M. Y.) USC

  23. Microarchitecture (Multi Cycle CPU) Combining the Memories Instruction and Data memories can be unified using a multiplexer for the address The Instruction and data need to be stored in registers Introduction to Computer Architecture, 2024 23/79 University of South Carolina (M. Y.) USC

  24. Microarchitecture (Multi Cycle CPU) Instruction Decoding Instruction and Data memories can be unified using a multiplexer for the address The Instruction and data need to be stored in registers Instructions are the same as before, so is the instruction decoder! Introduction to Computer Architecture, 2024 24/79 University of South Carolina (M. Y.) USC

  25. Microarchitecture (Multi Cycle CPU) ALU Instruction and Data memories can be unified using a multiplexer for the address The Instruction and data need to be stored in registers Instructions are the same as before, so is the instruction decoder! We can save adders by reusing ALU for all the additions Introduction to Computer Architecture, 2024 25/79 University of South Carolina (M. Y.) USC

  26. Therefore we break each instruction into multiple cycles The great advantage is that different instructions can have different run of cycles Microarchitecture (Multi Cycle CPU) Big Problem Instruction and Data memories can be unified using a multiplexer for the address The Instruction and data need to be stored in registers Since the instructions are the same, so is the instruction decoder We can save adders by reusing ALU for all the additions We have a problem! We can not perform multiple operation with one component in one cycle. Introduction to Computer Architecture, 2024 26/79 University of South Carolina (M. Y.) USC

  27. Microarchitecture (Multi Cycle CPU) Big Problem Instruction and Data memories can be unified using a multiplexer for the address The Instruction and data need to be stored in registers Since the instructions are the same, so is the instruction decoder We can save adders by reusing ALU for all the additions We have a problem! We can not perform multiple operation with one component in one cycle. Therefore we break each instruction into multiple cycles The great advantage is that different instructions can have different run of cycles Introduction to Computer Architecture, 2024 26/79 University of South Carolina (M. Y.) USC

  28. Microarchitecture (Multi Cycle CPU) Fetch Fetch Cycle: The instruction will be fetched from the current PC The fetched instruction will be stored into Instruction Register The current PC will be saved into old PC Introduction to Computer Architecture, 2024 27/79 University of South Carolina (M. Y.) USC

  29. Microarchitecture (Multi Cycle CPU) Decode Decode Cycle: Signals flow combinationally, no need to issue any control signal Introduction to Computer Architecture, 2024 28/79 University of South Carolina (M. Y.) USC

  30. Microarchitecture (Multi Cycle CPU) Load Instruction MemAdr Cycle: ALU must add the base address and the offset The address will be stored in ALUOut register Introduction to Computer Architecture, 2024 29/79 University of South Carolina (M. Y.) USC

  31. Microarchitecture (Multi Cycle CPU) Load Instruction MemRead Cycle: Memory must be read from the address stored in ALUOut The data will be stored in Data register Introduction to Computer Architecture, 2024 30/79 University of South Carolina (M. Y.) USC

  32. Microarchitecture (Multi Cycle CPU) Load Instruction MemWB Cycle: The data stored in Data reg must be written back into register file Introduction to Computer Architecture, 2024 31/79 University of South Carolina (M. Y.) USC

  33. Microarchitecture (Multi Cycle CPU) Updating PC We increment PC by 4 before fetching the next instruction ALU is not being used during Fetch cycle We can add necessary control signals to update PC during fetch cycle Introduction to Computer Architecture, 2024 32/79 University of South Carolina (M. Y.) USC

  34. Microarchitecture (Multi Cycle CPU) Load Instruction lw rd, imm(rs1) Introduction to Computer Architecture, 2024 33/79 University of South Carolina (M. Y.) USC

  35. Microarchitecture (Multi Cycle CPU) Load Instruction lw rd, imm(rs1) Introduction to Computer Architecture, 2024 34/79 University of South Carolina (M. Y.) USC

  36. Microarchitecture (Multi Cycle CPU) Load Instruction lw rd, imm(rs1) Introduction to Computer Architecture, 2024 35/79 University of South Carolina (M. Y.) USC

  37. Microarchitecture (Multi Cycle CPU) Load Instruction lw rd, imm(rs1) Introduction to Computer Architecture, 2024 36/79 University of South Carolina (M. Y.) USC

  38. Microarchitecture (Multi Cycle CPU) Load Instruction lw rd, imm(rs1) Introduction to Computer Architecture, 2024 37/79 University of South Carolina (M. Y.) USC

  39. Microarchitecture (Multi Cycle CPU) Store Instruction sw rs2, imm(rs1) Introduction to Computer Architecture, 2024 38/79 University of South Carolina (M. Y.) USC

  40. Microarchitecture (Multi Cycle CPU) Store Instruction sw rs2, imm(rs1) Introduction to Computer Architecture, 2024 39/79 University of South Carolina (M. Y.) USC

  41. Microarchitecture (Multi Cycle CPU) Store Instruction sw rs2, imm(rs1) Introduction to Computer Architecture, 2024 40/79 University of South Carolina (M. Y.) USC

  42. Microarchitecture (Multi Cycle CPU) Store Instruction sw rs2, imm(rs1) Introduction to Computer Architecture, 2024 41/79 University of South Carolina (M. Y.) USC

  43. Microarchitecture (Multi Cycle CPU) Store Instruction sw rs2, imm(rs1) Introduction to Computer Architecture, 2024 42/79 University of South Carolina (M. Y.) USC

  44. Microarchitecture (Multi Cycle CPU) R-Type Instruction add rd, rs1, rs2 Introduction to Computer Architecture, 2024 43/79 University of South Carolina (M. Y.) USC

  45. Microarchitecture (Multi Cycle CPU) R-Type Instruction add rd, rs1, rs2 Introduction to Computer Architecture, 2024 44/79 University of South Carolina (M. Y.) USC

  46. Microarchitecture (Multi Cycle CPU) R-Type Instruction add rd, rs1, rs2 Introduction to Computer Architecture, 2024 45/79 University of South Carolina (M. Y.) USC

  47. Microarchitecture (Multi Cycle CPU) R-Type Instruction add rd, rs1, rs2 Introduction to Computer Architecture, 2024 46/79 University of South Carolina (M. Y.) USC

  48. Microarchitecture (Multi Cycle CPU) R-Type Instruction add rd, rs1, rs2 Introduction to Computer Architecture, 2024 47/79 University of South Carolina (M. Y.) USC

  49. Microarchitecture (Multi Cycle CPU) I-Type Instruction addi rd, rs1, imm Introduction to Computer Architecture, 2024 48/79 University of South Carolina (M. Y.) USC

  50. Microarchitecture (Multi Cycle CPU) I-Type Instruction addi rd, rs1, imm Introduction to Computer Architecture, 2024 49/79 University of South Carolina (M. Y.) USC

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