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CSCE-212-Intro-To-Computer-Architecture-Lecture4-NumberRepresentationAndComputerArithmetic

CSCE-212-Introduction to Computer Architecture-Lecture4-Fall 2024-Mehdi Yaghouti

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CSCE-212-Intro-To-Computer-Architecture-Lecture4-NumberRepresentationAndComputerArithmetic

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  1. Number Representation and Computer Arithmetic University of South Carolina Introduction to Computer Architecture Fall, 2024 Instructor: Mehdi Yaghouti MehdiYaghouti@gmail.com Introduction to Computer Architecture, 2024 1/91 University of South Carolina (M. Y.) USC

  2. Binary Number Representation Decimal system: Base: 10 Digits: {0,1,2,3,4,5,6,7,8,9} Representation of a decimal number: Binary system: Base: 2 Digits: {0,1} Representation of a binary number: Introduction to Computer Architecture, 2024 2/91 University of South Carolina (M. Y.) USC

  3. Unsigned Binary Numbers N-bit binary number can represent 2Nnumbers, N-bits z }| { 1...1 Minimum: 0...0 N-bits z }| { Maximum: Range: ?0,...,2N− 1? Decimal to binary conversion Using common powers of 2 1,2,4,8,16,32,64,128,256,512,1024,2048,4096 Repeated Divisions Binary to decimal conversion (bN...b0)2=PN k=02kbk Introduction to Computer Architecture, 2024 3/91 University of South Carolina (M. Y.) USC

  4. Hexadecimal Representation Hexadecimal system: Base: 16 Digits: {0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F} Representation of a hexadecimal number: Correspondence between Hex digits and 4-bits PN Binary to Hexadecimal conversion Pack each 4-bit into a hex digit k=016k?P3 ? k=02kbk=PN/4 l=02lb(4∗k+l) Hexadecimal to Binary conversion Unpack each hex digits into 4-bits Introduction to Computer Architecture, 2024 4/91 University of South Carolina (M. Y.) USC

  5. Octal Representation Octal system: Base: 8 Digits: {0,1,2,3,4,5,6,7} Representation of an octal number: Correspondence between Octal digits and 3-bits PN Binary to Octal conversion Pack each 3-bit into a octal digit k=08k?P3 ? k=02kbk=PN/3 l=02lb(3∗k+l) Octal to Binary conversion Unpack each octal digits into 3-bits Introduction to Computer Architecture, 2024 5/91 University of South Carolina (M. Y.) USC

  6. Binary Addition Basic Rules: 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 10 (0 with a carry of 1) Steps for Adding Two Binary Numbers: 1 Aligning the Numbers 2 Adding digit by digit, starting from LSB 3 Carry Over: If the sum is 2 (binary 10), carry the 1 to the next column 4 Overflow: The carry out of the leftmost digit Care must be taken as registers have constant number of bits Introduction to Computer Architecture, 2024 6/91 University of South Carolina (M. Y.) USC

  7. Binary Subtraction Basic Rules: 0 − 0 = 0 1 − 0 = 1 1 − 1 = 0 0 − 1 = 1 (with a borrow of 1 from the next higher bit) Steps for Subtracting Two Binary Numbers: 1 Aligning the numbers 2 Subtracting digit by digit, starting from LSB 3 Borrowing: When subtracting 1 from 0, borrow 1 from the next higher bit 4 Borrow in: If a borrow needed beyond the leftmost digit, the result is negative Introduction to Computer Architecture, 2024 7/91 University of South Carolina (M. Y.) USC

  8. Sign/Magnitude Number System Sign/Magnitude: Sign bit: Most significant bit ( − → 1 + → 0 Example: +23 = 00010111 −23 = 10010111 (sign/magnitude representation) Spans the range?−?2N−1− 1?,2N−1− 1? Zero has two representations +0, −0 Troublesome to use in fast arithmetic circuits Ordinary addition doesn’t work on sign included representation Introduction to Computer Architecture, 2024 8/91 University of South Carolina (M. Y.) USC

  9. Two’s Complement Number System Two’s Complement system: N-bits Two’s complement representation N−2 X (bN−1...b0)2= −bN2N−1+ 2kbk k=0 Spans the asymmetric range?−2N−1,2N−1− 1? representation Sign bit: Most significant bit ( − → 1 Ordinary addition works well on sign included + → 0 Zero has only one representation Two’s complement is the most accepted one for fast arithmetic circuits Introduction to Computer Architecture, 2024 9/91 University of South Carolina (M. Y.) USC

  10. Two’s Complement System Negation Rule 1 Negate all the bits 2 Add 1 Example: negated − − − − → 11101000 negated − − − − → 00010110 +1 − → 11101001 = −23 +1 − → 00010111 = +23 +23 = 00010111 −23 = 11101001 Addition/Subtraction 47 − 11 = 36 −47 + 11 = −36 11010001 +00001011 11011100 −47 − 11 = −58 11010001 + 11110101 111000110 47 + 11 = 58 00101111 + 11110101 100100100 00101111 +00001011 00111010 Introduction to Computer Architecture, 2024 10/91 University of South Carolina (M. Y.) USC

  11. Overflow Unsigned Numbers Overflow occurs when there is a carry out of the MSB column Example: 7 + 12 = 19 0111 + 1100 11011 Signed Numbers (Two’s complement) Overflow can only happen when two numbers have the same sign bit Overflow occurs when the result has the opposite sign bit Example: −7 − 4 = −11 7 + 4 = 11 0111 +0100 1011 1001 + 1100 10101 Introduction to Computer Architecture, 2024 11/91 University of South Carolina (M. Y.) USC

  12. Adder Half Adder: {cout,S} = A + B Introduction to Computer Architecture, 2024 12/91 University of South Carolina (M. Y.) USC

  13. Adder Half Adder: {cout,S} = A + B Full Adder: {cout,S} = A + B + cin Generate: G = A • B Propagate: P = A ⊕ B Introduction to Computer Architecture, 2024 13/91 University of South Carolina (M. Y.) USC

  14. Adder Half Adder: {cout,S} = A + B Full Adder: {cout,S} = A + B + cin Generate: G = A • B Propagate: P = A ⊕ B Delay: max{2tpd xor,tpd xor+ tpd or+ tpd and} Introduction to Computer Architecture, 2024 14/91 University of South Carolina (M. Y.) USC

  15. Adder Half Adder: {cout,S} = A + B Full Adder: {cout,S} = A + B + cin Generate: G = A • B Propagate: P = A ⊕ B Delay: max{2tpd xor,tpd xor+ tpd or+ tpd and} tFA= tpd or3+ tpd and Introduction to Computer Architecture, 2024 15/91 University of South Carolina (M. Y.) USC

  16. SystemVerilog (Optional) Implementation using P and G signals The second alternative Introduction to Computer Architecture, 2024 16/91 University of South Carolina (M. Y.) USC

  17. Ripple-Carry Adder Carry Propagate Adder (CPA): Sums N-bit inputs Ripple-Carry Adder: Chains N full adders Delay: tpd rca= NttFA Introduction to Computer Architecture, 2024 17/91 University of South Carolina (M. Y.) USC

  18. Look-ahead Block Generate: Gj:i= Gj+ PjGj−1:i Propagate: Pj:i= PjPj−1... Pi Carry: Cout= Gj:i+ Pj:iCin Delay: tpg= max{tAND,tXOR} tpg block= 3 (tAND+ tOR) Introduction to Computer Architecture, 2024 18/91 University of South Carolina (M. Y.) USC

  19. Carry Look-Ahead Adder Generate: Gj:i= Gj+ PjGj−1:i Propagate: Pj:i= PjPj−1... Pi Delay: tcla= tpg+ tpg block+?N k− 1?tand or+ ktFA Introduction to Computer Architecture, 2024 19/91 University of South Carolina (M. Y.) USC

  20. Prefix Adder (Optional) Generate: Gi:j= Gi:k+ Pi:kGk−1:j Propagate: Pi:j= Pi:kPk−1:j Delay: tPA= tpg+ tpg prefixlog2N + tXOR Introduction to Computer Architecture, 2024 20/91 University of South Carolina (M. Y.) USC

  21. Question Compare the delays of a 64-bit ripple-carry, a 64-bit carry-lookahead with 4-bit blocks and a 64-bit prefix adder. Introduction to Computer Architecture, 2024 21/91 University of South Carolina (M. Y.) USC

  22. SystemVerilog (Optional) keyword parameter Using high level description we leave the implementation to the synthesizer Introduction to Computer Architecture, 2024 22/91 University of South Carolina (M. Y.) USC

  23. Subtraction Two’s Complement Subtraction: A − B = A + B + 1 Introduction to Computer Architecture, 2024 23/91 University of South Carolina (M. Y.) USC

  24. Comparators Compares two binary inputs Using XNOR to check equality Using subtraction and check the sign bit Introduction to Computer Architecture, 2024 24/91 University of South Carolina (M. Y.) USC

  25. Multiplication Binary multiplication is based on two basic operations: Generation of partial products Accumulation The multiplication of two N-bits number is in general a 2N-bits number Introduction to Computer Architecture, 2024 25/91 University of South Carolina (M. Y.) USC

  26. Multiplication Binary multiplication is based on two basic operations: Generation of partial products Accumulation The multiplication of two N-bits number is a 2N-bits number in general Each partial product is either zero or the multiplicand Introduction to Computer Architecture, 2024 26/91 University of South Carolina (M. Y.) USC

  27. Multiplication Binary multiplication is based on two basic operations: Generation of partial products Accumulation The multiplication of two N-bits number is a 2N-bits number in general Each partial product is either zero or the multiplicand Partial products can be generated by using AND gates Introduction to Computer Architecture, 2024 27/91 University of South Carolina (M. Y.) USC

  28. Sequential Multiplier Binary multiplication can be done in a sequential manner Sequential multiplication is based on two observations Each partial product is either zero of the multiplicand The partial products can be accumulated incrementally It can be best understood by an example Introduction to Computer Architecture, 2024 28/91 University of South Carolina (M. Y.) USC

  29. Sequential Multiplier Binary multiplication can be done in a sequential manner Sequential multiplication is based on two observations Each partial product is either zero of the multiplicand The partial products can be accumulated incrementally It can be best understood by an example Introduction to Computer Architecture, 2024 29/91 University of South Carolina (M. Y.) USC

  30. Sequential Multiplier Binary multiplication can be done in a sequential manner Sequential multiplication is based on two observations Each partial product is either zero of the multiplicand The partial products can be accumulated incrementally It can be best understood by an example Introduction to Computer Architecture, 2024 30/91 University of South Carolina (M. Y.) USC

  31. Sequential Multiplier Binary multiplication can be done in a sequential manner Sequential multiplication is based on two observations Each partial product is either zero of the multiplicand The partial products can be accumulated incrementally It can be best understood by an example Introduction to Computer Architecture, 2024 31/91 University of South Carolina (M. Y.) USC

  32. Sequential Multiplier Binary multiplication can be done in a sequential manner Sequential multiplication is based on two observations Each partial product is either zero of the multiplicand The partial products can be accumulated incrementally It can be best understood by an example Introduction to Computer Architecture, 2024 32/91 University of South Carolina (M. Y.) USC

  33. Sequential Multiplier (Optional) Binary multiplication can be done in a sequential manner Sequential multiplication is based on two observations Each partial product is either zero of the multiplicand The partial products can be accumulated incrementally The process can be described with the following flowchart Introduction to Computer Architecture, 2024 33/91 University of South Carolina (M. Y.) USC

  34. Sequential Multiplier (Optional) Hardware Architecure M holds the multplicand Q holds the multiplier A holds the partial products summation Introduction to Computer Architecture, 2024 34/91 University of South Carolina (M. Y.) USC

  35. SystemVerilog Project: Sequential Multiplier (Optional) Design a system verilog module to perform the sequential multiplication Your module must have the following interface The project is optional and has extra bonus The following files must be uploaded The multiplier module: Seq Multiplier.sv Testbench: Simulated Waveforms: Waveforms.pdf Testbench.sv Introduction to Computer Architecture, 2024 35/91 University of South Carolina (M. Y.) USC

  36. Division (Optional) Binary division is based on two basic operations: Generation of partial remainders Subtraction and shifting The quotient in division of two N-bits number is in general a N-bits number Introduction to Computer Architecture, 2024 36/91 University of South Carolina (M. Y.) USC

  37. Division (Optional) Binary division is based on two basic operations: Generation of partial remainders Subtraction and shifting The quotient in division of two N-bits number is in general a N-bits number R′← 0 for i =(N − 1) to 0 R ← {R′<< 1,Ai} D = R − B if D < 0 Qi← 0 R′← R else Qi← 1 R′← D R′← R Introduction to Computer Architecture, 2024 37/91 University of South Carolina (M. Y.) USC

  38. Division (Optional) Binary division is based on two basic operations: Generation of partial remainders Subtraction and shifting The quotient in division of two N-bits number is in general a N-bits number R′← 0 for i =(N − 1) to 0 R ← {R′<< 1,Ai} D = R − B if D < 0 Qi← 0 R′← R else Qi← 1 R′← D R′← R Introduction to Computer Architecture, 2024 38/91 University of South Carolina (M. Y.) USC

  39. Division (Optional) Hardware implementation of binary division Introduction to Computer Architecture, 2024 39/91 University of South Carolina (M. Y.) USC

  40. ALU Performs mathematical and logical operations ALUControl specifies function Common Flags: N, Z, C, V Overflow detection Magnitude comparison depends on signed/unsigned Introduction to Computer Architecture, 2024 40/91 University of South Carolina (M. Y.) USC

  41. Shifters Logical left and right shifts Introduction to Computer Architecture, 2024 41/91 University of South Carolina (M. Y.) USC

  42. Shifters Logical shifter Arithmetic shifter Arithmetic shift left multiplies by 2 Arithmetic shift right divides by 2 Overflow must be taken care of N-bit shifter can be built from N, N : 1 MUXs Introduction to Computer Architecture, 2024 42/91 University of South Carolina (M. Y.) USC

  43. Shift Registers Shift registers act as serial-to-parallel converters The input is provided serially at Sin After N cycles, the last N inputs appear at Q0...QN−1 Introduction to Computer Architecture, 2024 43/91 University of South Carolina (M. Y.) USC

  44. SystemVerilog (Optional) A typical ALU supporting add, sub, and, or, slt, sll, srl It has generates Zero and oVerflow signals Introduction to Computer Architecture, 2024 44/91 University of South Carolina (M. Y.) USC

  45. Shift Registers Shift registers act as serial-to-parallel converters The input is provided serially at Sin After N cycles, the last N inputs appear at Q0...QN−1 Shift registers with parallel load can act in reverse The input D0...DN−1 is loaded in parallel Takes N cycles to shift out as parallel-to-serial converter Introduction to Computer Architecture, 2024 45/91 University of South Carolina (M. Y.) USC

  46. Counters N-bit counter composed of an adder and a resettable register On each cycle, the counter adds 1 to the value stored in the register They are commonly used for dividing the clock frequency Introduction to Computer Architecture, 2024 46/91 University of South Carolina (M. Y.) USC

  47. Rational Numbers ( Fixed Point Representation ) Fixed-point notation has an implied binary point Introduction to Computer Architecture, 2024 47/91 University of South Carolina (M. Y.) USC

  48. Rational Numbers ( Fixed Point Representation ) Fixed-point notation has an implied binary point Decimal fraction to Binary conversion Common negative power of two 0.5, 0.25, 0.125, 0.0625, 0.03125, ··· Repeated multiplication by 2 Introduction to Computer Architecture, 2024 48/91 University of South Carolina (M. Y.) USC

  49. Rational Numbers ( Fixed Point Representation ) Fixed-point notation has an implied binary point Decimal fraction to Binary conversion Common negative power of two 0.5, 0.25, 0.125, 0.0625, 0.03125, ··· Repeated multiplication by 2 Binary to decimal conversion (bN...bkˆbk−1...b0)2=PN i=02i−kbi−k Introduction to Computer Architecture, 2024 49/91 University of South Carolina (M. Y.) USC

  50. Signed Rational Numbers ( Fixed Point Representation ) Sign/Magnitude Introduction to Computer Architecture, 2024 50/91 University of South Carolina (M. Y.) USC

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