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CSCE-212-Intro-To-Computer-Architecture-Lecture2-ReviewDigitalDesignCL

CSCE-212 Introduction to Computer Architecture Lecture-2 (Fall 2024-Mehdi Yaghouti)

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CSCE-212-Intro-To-Computer-Architecture-Lecture2-ReviewDigitalDesignCL

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  1. Review on Digital Design (Combinational Circuits) University of South Carolina Introduction to Computer Architecture Fall, 2024 Instructor: Mehdi Yaghouti MehdiYaghouti@gmail.com Introduction to Computer Architecture, 2024 1/52 University of South Carolina (M. Y.) USC

  2. Fundamental Logic Gates Fundamental: AND, OR, and NOT are the core building blocks of digital logic. Universal: They can implement all possible logical operations. Introduction to Computer Architecture, 2024 2/52 University of South Carolina (M. Y.) USC

  3. Boolean Algebra The set of logical axioms/rules governing the manipulation binary variables. Introduction to Computer Architecture, 2024 3/52 University of South Carolina (M. Y.) USC

  4. Manipulation Rules Primitive rules Introduction to Computer Architecture, 2024 4/52 University of South Carolina (M. Y.) USC

  5. Associativity (B • C) • D = B • (C • D) Distributivity (B • C) + (B • D) = B • (C + D) Covering (B + C) + D = B + (C + D) (B + C) • (B + D) = B + (C • D) B • (B + C) = B B + (B • C) = B Combining (B • C) + (B • C) = B (B + C) • (B + C) = B Consensus (B • C) + (B • D) + (C • D) = (B • C) + (B • D) (B + C) • (B + D) • (C + D) = (B + C) • (B • D) De Morgan’s Theorem B0• B1• B2• ··· = B0+ B1+ B2+ ··· B0+ B1+ B2+ ··· = B0• B1• B2• ··· Manipulation Rules Commutativity B • C = C • B B + C = C + B Introduction to Computer Architecture, 2024 5/52 University of South Carolina (M. Y.) USC

  6. Distributivity (B • C) + (B • D) = B • (C + D) Covering (B + C) • (B + D) = B + (C • D) B • (B + C) = B B + (B • C) = B Combining (B • C) + (B • C) = B (B + C) • (B + C) = B Consensus (B • C) + (B • D) + (C • D) = (B • C) + (B • D) (B + C) • (B + D) • (C + D) = (B + C) • (B • D) De Morgan’s Theorem B0• B1• B2• ··· = B0+ B1+ B2+ ··· B0+ B1+ B2+ ··· = B0• B1• B2• ··· Manipulation Rules Commutativity B • C = C • B B + C = C + B Associativity (B • C) • D = B • (C • D) (B + C) + D = B + (C + D) Introduction to Computer Architecture, 2024 5/52 University of South Carolina (M. Y.) USC

  7. Covering B • (B + C) = B B + (B • C) = B Combining (B • C) + (B • C) = B (B + C) • (B + C) = B Consensus (B • C) + (B • D) + (C • D) = (B • C) + (B • D) (B + C) • (B + D) • (C + D) = (B + C) • (B • D) De Morgan’s Theorem B0• B1• B2• ··· = B0+ B1+ B2+ ··· B0+ B1+ B2+ ··· = B0• B1• B2• ··· Manipulation Rules Commutativity B • C = C • B B + C = C + B Associativity (B • C) • D = B • (C • D) Distributivity (B • C) + (B • D) = B • (C + D) (B + C) + D = B + (C + D) (B + C) • (B + D) = B + (C • D) Introduction to Computer Architecture, 2024 5/52 University of South Carolina (M. Y.) USC

  8. Combining (B • C) + (B • C) = B (B + C) • (B + C) = B Consensus (B • C) + (B • D) + (C • D) = (B • C) + (B • D) (B + C) • (B + D) • (C + D) = (B + C) • (B • D) De Morgan’s Theorem B0• B1• B2• ··· = B0+ B1+ B2+ ··· B0+ B1+ B2+ ··· = B0• B1• B2• ··· Manipulation Rules Commutativity B • C = C • B B + C = C + B Associativity (B • C) • D = B • (C • D) Distributivity (B • C) + (B • D) = B • (C + D) Covering (B + C) + D = B + (C + D) (B + C) • (B + D) = B + (C • D) B • (B + C) = B B + (B • C) = B Introduction to Computer Architecture, 2024 5/52 University of South Carolina (M. Y.) USC

  9. Consensus (B • C) + (B • D) + (C • D) = (B • C) + (B • D) (B + C) • (B + D) • (C + D) = (B + C) • (B • D) De Morgan’s Theorem B0• B1• B2• ··· = B0+ B1+ B2+ ··· B0+ B1+ B2+ ··· = B0• B1• B2• ··· Manipulation Rules Commutativity B • C = C • B B + C = C + B Associativity (B • C) • D = B • (C • D) Distributivity (B • C) + (B • D) = B • (C + D) Covering (B + C) + D = B + (C + D) (B + C) • (B + D) = B + (C • D) B • (B + C) = B B + (B • C) = B Combining (B • C) + (B • C) = B (B + C) • (B + C) = B Introduction to Computer Architecture, 2024 5/52 University of South Carolina (M. Y.) USC

  10. De Morgan’s Theorem B0• B1• B2• ··· = B0+ B1+ B2+ ··· B0+ B1+ B2+ ··· = B0• B1• B2• ··· Manipulation Rules Commutativity B • C = C • B B + C = C + B Associativity (B • C) • D = B • (C • D) Distributivity (B • C) + (B • D) = B • (C + D) Covering (B + C) + D = B + (C + D) (B + C) • (B + D) = B + (C • D) B • (B + C) = B B + (B • C) = B Combining (B • C) + (B • C) = B (B + C) • (B + C) = B Consensus (B • C) + (B • D) + (C • D) = (B • C) + (B • D) (B + C) • (B + D) • (C + D) = (B + C) • (B • D) Introduction to Computer Architecture, 2024 5/52 University of South Carolina (M. Y.) USC

  11. Manipulation Rules Commutativity B • C = C • B B + C = C + B Associativity (B • C) • D = B • (C • D) Distributivity (B • C) + (B • D) = B • (C + D) Covering (B + C) + D = B + (C + D) (B + C) • (B + D) = B + (C • D) B • (B + C) = B B + (B • C) = B Combining (B • C) + (B • C) = B (B + C) • (B + C) = B Consensus (B • C) + (B • D) + (C • D) = (B • C) + (B • D) (B + C) • (B + D) • (C + D) = (B + C) • (B • D) De Morgan’s Theorem B0• B1• B2• ··· = B0+ B1+ B2+ ··· B0+ B1+ B2+ ··· = B0• B1• B2• ··· Introduction to Computer Architecture, 2024 5/52 University of South Carolina (M. Y.) USC

  12. Manipulation Rules Theorems Introduction to Computer Architecture, 2024 6/52 University of South Carolina (M. Y.) USC

  13. Common Logic Gates Introduction to Computer Architecture, 2024 7/52 University of South Carolina (M. Y.) USC

  14. Sequential Circuits Input terminals Output terminals Has Memory Synchronous/Asynchronous Functional specification Timing specification Digital Circuits Combinational Circuits Input terminals Output terminals Memoryless No Cyclic path Functional specification Timing specification Introduction to Computer Architecture, 2024 8/52 University of South Carolina (M. Y.) USC

  15. Digital Circuits Combinational Circuits Input terminals Output terminals Memoryless No Cyclic path Functional specification Timing specification Sequential Circuits Input terminals Output terminals Has Memory Synchronous/Asynchronous Functional specification Timing specification Introduction to Computer Architecture, 2024 8/52 University of South Carolina (M. Y.) USC

  16. Combinational Circuits Functional Specification Circuit Diagram Introduction to Computer Architecture, 2024 9/52 University of South Carolina (M. Y.) USC

  17. Combinational Circuits Functional Specification Circuit Diagram Boolean Equation Introduction to Computer Architecture, 2024 10/52 University of South Carolina (M. Y.) USC

  18. Combinational Circuits Functional Specification Circuit Diagram Boolean Equation F = ABC +(A+B+C)(AB + AC + BC) G = (AB + AC + BC) Introduction to Computer Architecture, 2024 11/52 University of South Carolina (M. Y.) USC

  19. Combinational Circuits Functional Specification Circuit Diagram Boolean Equation Truth Table F = ABC +(A+B+C)(AB + AC + BC) G = (AB + AC + BC) Introduction to Computer Architecture, 2024 12/52 University of South Carolina (M. Y.) USC

  20. Combinational Circuits Functional Specification Circuit Diagram Boolean Equation Truth Table F = ABC +(A+B+C)(AB + AC + BC) G = (AB + AC + BC) Introduction to Computer Architecture, 2024 13/52 University of South Carolina (M. Y.) USC

  21. Combinational Circuits Functional Specification Circuit Diagram Boolean Equation Truth Table F = ABC +(A+B+C)(AB + AC + BC) G = (AB + AC + BC) F =¯A¯BC +¯AB¯C + A¯B¯C + ABC G =¯ABC + A¯BC + AB¯C + ABC Introduction to Computer Architecture, 2024 14/52 University of South Carolina (M. Y.) USC

  22. Combinational Circuits Functional Specification Circuit Diagram Truth Table Boolean Equation Hardware Description Language F = ABC +(A+B+C)(AB + AC + BC) G = (AB + AC + BC) F =¯A¯BC +¯AB¯C + A¯B¯C + ABC G =¯ABC + A¯BC + AB¯C + ABC Introduction to Computer Architecture, 2024 15/52 University of South Carolina (M. Y.) USC

  23. Logic Minimization / K-Maps Boolean Algebra as simplification rules G =¯ABC + A¯BC + AB¯C + ABC Introduction to Computer Architecture, 2024 16/52 University of South Carolina (M. Y.) USC

  24. Logic Minimization / K-Maps Boolean Algebra as simplification rules G =¯ABC + A¯BC + AB¯C + ABC =?¯ABC + ABC?+?A¯BC + ABC?+?AB¯C + ABC? Introduction to Computer Architecture, 2024 17/52 University of South Carolina (M. Y.) USC

  25. Logic Minimization / K-Maps Boolean Algebra as simplification rules G =¯ABC + A¯BC + AB¯C + ABC =?¯ABC + ABC?+?A¯BC + ABC?+?AB¯C + ABC? =?¯A + A?BC + A?¯B + B?C + AB?¯C + C? Introduction to Computer Architecture, 2024 18/52 University of South Carolina (M. Y.) USC

  26. Logic Minimization / K-Maps Boolean Algebra as simplification rules G =¯ABC + A¯BC + AB¯C + ABC =?¯ABC + ABC?+?A¯BC + ABC?+?AB¯C + ABC? = BC + AC + AB =?¯A + A?BC + A?¯B + B?C + AB?¯C + C? Introduction to Computer Architecture, 2024 19/52 University of South Carolina (M. Y.) USC

  27. Logic Minimization / K-Maps Boolean Algebra as simplification rules G =¯ABC + A¯BC + AB¯C + ABC =?¯ABC + ABC?+?A¯BC + ABC?+?AB¯C + ABC? = BC + AC + AB =?¯A + A?BC + A?¯B + B?C + AB?¯C + C? Introduction to Computer Architecture, 2024 20/52 University of South Carolina (M. Y.) USC

  28. Hardware Description Languages Schematic-level circuit design is labor-intensive and error-prone Manual simplification of truth tables and FSMs is cumbersome Started from 1990s, designers shifted to higher abstraction levels CAD tools now optimize gates from logical functions HDLs are used for specifications Leading HDLs: Verilog and VHDL SystemVerilog extends Verilog with advanced features while maintaining backward compatibility Two main phases: Simulation Testing the module in a software environment to verify correct behavior Synthesis Converting the high-level design into a gate-level representation Synthesis varies by the target platform The Best way to learn HDL is by examples Introduction to Computer Architecture, 2024 21/52 University of South Carolina (M. Y.) USC

  29. SystemVerilog Combinational circuit as an input/output module Introduction to Computer Architecture, 2024 22/52 University of South Carolina (M. Y.) USC

  30. SystemVerilog Declaring internal wires Introduction to Computer Architecture, 2024 23/52 University of South Carolina (M. Y.) USC

  31. SystemVerilog Logical operation in SystemVerilog Introduction to Computer Architecture, 2024 24/52 University of South Carolina (M. Y.) USC

  32. SystemVerilog Operators Operations precedence in SystemVerilog What would happen if we change the order of the two assign lines? Introduction to Computer Architecture, 2024 25/52 University of South Carolina (M. Y.) USC

  33. SystemVerilog SystemVerilog code Synthesized circuit Introduction to Computer Architecture, 2024 26/52 University of South Carolina (M. Y.) USC

  34. SystemVerilog (Testbench) Testbench Introduction to Computer Architecture, 2024 27/52 University of South Carolina (M. Y.) USC

  35. Seven-Segment Decoder 4-inputs 7-outputs Each segment is only a function of 4-inputs Introduction to Computer Architecture, 2024 28/52 University of South Carolina (M. Y.) USC

  36. Seven-Segment Decoder 4-inputs 7-outputs Each segment is only a function of 4-inputs Sa=D3D2D1D0+ D3D2D1D0+ D3D2D1D0D3D2D1D0 + D3D2D1D0+ D3D2D1D0+ D3D2D1D0+ D3D2D1D0 Introduction to Computer Architecture, 2024 29/52 University of South Carolina (M. Y.) USC

  37. Seven-Segment Decoder 4-inputs 7-outputs Each segment is only a function of 4-inputs Sa=D3D2D1D0+ D3D2D1D0+ D3D2D1D0D3D2D1D0 + D3D2D1D0+ D3D2D1D0+ D3D2D1D0+ D3D2D1D0 Introduction to Computer Architecture, 2024 30/52 University of South Carolina (M. Y.) USC

  38. SystemVerilog Bundle notation [n : 0] always comb and case statement Introduction to Computer Architecture, 2024 31/52 University of South Carolina (M. Y.) USC

  39. SystemVerilog Testbench Introduction to Computer Architecture, 2024 32/52 University of South Carolina (M. Y.) USC

  40. Multiplexer A N : 1 Mux chooses 1 out of N inputs 2:1 Mux as a combinational circuit Introduction to Computer Architecture, 2024 33/52 University of South Carolina (M. Y.) USC

  41. SystemVerilog A 2 : 1 Mux can be easily implemented using ternary operator Introduction to Computer Architecture, 2024 34/52 University of South Carolina (M. Y.) USC

  42. Multiplexer A N : 1 Mux chooses 1 out of N inputs 2 : 1 Mux as a combinational circuit 4 : 1 Mux implemented based on description Introduction to Computer Architecture, 2024 35/52 University of South Carolina (M. Y.) USC

  43. Multiplexer A 2n: 1 Mux can be implemented as a binary tree n cascaded layer is needed Introduction to Computer Architecture, 2024 36/52 University of South Carolina (M. Y.) USC

  44. SystemVerilog ternary operators can be combined to implement larger Mux Introduction to Computer Architecture, 2024 37/52 University of South Carolina (M. Y.) USC

  45. Tristate Buffer X designates an illegal or unknown logic value Introduction to Computer Architecture, 2024 38/52 University of South Carolina (M. Y.) USC

  46. Tristate Buffer X designates an illegal or unknown logic value Z designates a high impedance or floating terminal X and Z are neither 0 nor 1 logical level Tristate buffer possible output states: 1, 0, and Z Introduction to Computer Architecture, 2024 39/52 University of South Carolina (M. Y.) USC

  47. Tristate Buffer X designates an illegal or unknown logic value Z designates a high impedance or floating terminal X and Z are neither 0 nor 1 logical level Tristate buffer possible output states: 1, 0, and Z They are commonly used for bus connections Introduction to Computer Architecture, 2024 40/52 University of South Carolina (M. Y.) USC

  48. Tristate Buffer X designates an illegal or unknown logic value Z designates a high impedance or floating terminal X and Z are neither 0 nor 1 logical level Tristate buffer possible output states: 1, 0, and Z They are commonly used for bus connections Mux implementation with Tristate buffers Introduction to Computer Architecture, 2024 41/52 University of South Carolina (M. Y.) USC

  49. Tristate Buffer Tristate variables must be declared as tri rather than logic Introduction to Computer Architecture, 2024 42/52 University of South Carolina (M. Y.) USC

  50. Decoder Decodes a N-bits combination into a one-hot output A N : 2Ndecoder has N inputs and 2Noutputs Introduction to Computer Architecture, 2024 43/52 University of South Carolina (M. Y.) USC

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