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Arithmetic Building Blocks. A Generic Digital Processor. Building Blocks for Digital Architectures. Arithmetic unit. Bit-sliced datapath. adder. -. (. , multiplier, . shifter, comparator, etc.). Memory. - RAM, ROM, Buffers, Shift registers. Control.

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slide3

Building Blocks for Digital Architectures

Arithmetic unit

Bit-sliced datapath

adder

-

(

, multiplier,

shifter, comparator, etc.)

Memory

- RAM, ROM, Buffers, Shift registers

Control

- Finite state machine (PLA, random logic.)

- Counters

Interconnect

- Switches

- Arbiters

- Bus

the mirror adder
The Mirror Adder
  • The NMOS and PMOS chains are completely symmetrical. This guarantees identical rising and falling transitions if the NMOS and PMOS devices are properly sized. A maximum of two series transistors can be observed in the carry-generation circuitry.
  • When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion capacitances is particularly important.
  • The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell .
  • The transistors connected to Ci are placed closest to the output.
  • Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size.
np cmos adder17
NP-CMOS Adder

C

o1

S

1

A

1

B

1

S

0

A

0

B

0

C

i0