Ee 5340 semiconductor device theory lecture 27 fall 2003
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EE 5340 Semiconductor Device Theory Lecture 27 - Fall 2003 Professor Ronald L. Carter [email protected] http://www.uta.edu/ronc n-channel enhancement MOSFET in ohmic region 0< V T < V G Channel V S = 0 0< V D < V DS,sat E Ox,x > 0 e - e - e - e - e - n+ n+ Depl Reg p-substrate

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Ee 5340 semiconductor device theory lecture 27 fall 2003 l.jpg

EE 5340Semiconductor Device TheoryLecture 27 - Fall 2003

Professor Ronald L. Carter

[email protected]

http://www.uta.edu/ronc


N channel enhancement mosfet in ohmic region l.jpg
n-channel enhancementMOSFET in ohmic region

0< VT< VG

Channel

VS = 0

0< VD< VDS,sat

EOx,x> 0

e-e- e- e- e-

n+

n+

Depl Reg

p-substrate

Acceptors

VB < 0


Fully biased n channel v t calc l.jpg
Fully biased n-channel VT calc


Fully biased p channel v t calc l.jpg
Fully biased p-channel VT calc


I v relation for n mos ohmic reg l.jpg
I-V relation for n-MOS (ohmic reg)

ohmic

ID

non-physical

ID,sat

saturated

VDS

VDS,sat


Universal drain characteristic l.jpg
Universal draincharacteristic

ID

VGS=VT+3V

9ID1

ohmic

saturated, VDS>VGS-VT

VGS=VT+2V

4ID1

VGS=VT+1V

ID1

VDS


Substrate bias effect on v t body effect l.jpg
Substrate bias effect on VT (body-effect)


Body effect data l.jpg
Body effect data

Fig 9.9**


Low field ohmic characteristics l.jpg
Low field ohmiccharacteristics


Mosfet circuit parameters l.jpg
MOSFET circuitparameters


Mosfet circuit parameters cont l.jpg
MOSFET circuitparameters (cont)


Mosfet equivalent circuit elements l.jpg
MOSFET equivalentcircuit elements

Fig 10.51*


Mos small signal equivalent circuit l.jpg
MOS small-signal equivalent circuit

Fig 10.52*


Mos channel length modulation l.jpg
MOS channel-length modulation

Fig 11.5*


Analysis of channel length modulation l.jpg
Analysis of channellength modulation


Channel length mod ulated drain char l.jpg
Channel length mod-ulated drain char

Fig 11.6*


Associating the output conductance l.jpg
Associating theoutput conductance

ID

ID,sat

VDS

VDS,sat


Implanted n channel enhance ment mosfet ohmic region l.jpg
Implanted n-channel enhance-ment MOSFET (ohmic region)

0< VT< VG

e- channel ele + implant ion

Channel

VS = 0

0< VD< VDS,sat

EOx,x> 0

n+

n+

e-e- e- e- e-

++++++++++++

Depl Reg

p-substrate

Acceptors

VB < 0


Ion implantation l.jpg

Range

Si & SiO2

Al

Si3N4

DRP

Si

Al & SiO2

Si3N4

Ion implantation*



Calculating x i and d v t l.jpg
Calculating xi andDVT


References l.jpg
References

* Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997.

**Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986


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