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EE 5340 Semiconductor Device Theory Lecture 27 - Fall 2003

EE 5340 Semiconductor Device Theory Lecture 27 - Fall 2003 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc n-channel enhancement MOSFET in ohmic region 0< V T < V G Channel V S = 0 0< V D < V DS,sat E Ox,x > 0 e - e - e - e - e - n+ n+ Depl Reg p-substrate

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EE 5340 Semiconductor Device Theory Lecture 27 - Fall 2003

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  1. EE 5340Semiconductor Device TheoryLecture 27 - Fall 2003 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc

  2. n-channel enhancementMOSFET in ohmic region 0< VT< VG Channel VS = 0 0< VD< VDS,sat EOx,x> 0 e-e- e- e- e- n+ n+ Depl Reg p-substrate Acceptors VB < 0

  3. Fully biased n-channel VT calc

  4. Fully biased p-channel VT calc

  5. I-V relation for n-MOS (ohmic reg) ohmic ID non-physical ID,sat saturated VDS VDS,sat

  6. Universal draincharacteristic ID VGS=VT+3V 9ID1 ohmic saturated, VDS>VGS-VT VGS=VT+2V 4ID1 VGS=VT+1V ID1 VDS

  7. Substrate bias effect on VT (body-effect)

  8. Body effect data Fig 9.9**

  9. Low field ohmiccharacteristics

  10. MOSFET circuitparameters

  11. MOSFET circuitparameters (cont)

  12. MOSFET equivalentcircuit elements Fig 10.51*

  13. MOS small-signal equivalent circuit Fig 10.52*

  14. MOS channel-length modulation Fig 11.5*

  15. Analysis of channellength modulation

  16. Channel length mod-ulated drain char Fig 11.6*

  17. Associating theoutput conductance ID ID,sat VDS VDS,sat

  18. Implanted n-channel enhance-ment MOSFET (ohmic region) 0< VT< VG e- channel ele + implant ion Channel VS = 0 0< VD< VDS,sat EOx,x> 0 n+ n+ e-e- e- e- e- ++++++++++++ Depl Reg p-substrate Acceptors VB < 0

  19. Range Si & SiO2 Al Si3N4 DRP Si Al & SiO2 Si3N4 Ion implantation*

  20. “Dotted box” approx**

  21. Calculating xi andDVT

  22. References * Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986

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