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CS 161 Chapter 8 - I/O Lecture 17 Anatomy: 5 components of any Computer Keyboard, Mouse Computer Processor (active) Devices Memory (passive) (where programs, data live when running) Disk (where programs, data live when not running) Input Control (“brain”) Output

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anatomy 5 components of any computer
Anatomy: 5 components of any Computer

Keyboard, Mouse

Computer

Processor

(active)

Devices

Memory

(passive)

(where

programs,

data live

when

running)

Disk(where

programs,

data live when not running)

Input

Control

(“brain”)

Output

Datapath

(“brawn”)

Display, Printer

i o device examples and speeds
I/O Device Examples and Speeds
  • I/O Speed: bytes transferred per second(from mouse to display: million-to-1)
  • Device Behavior Partner Data Rate (Mbit/sec)

Keyboard Input Human 0.0001

Mouse Input Human 0.0038

Laser Printer Output Human 3.2.000

Magnetic Disk Storage Machine 240-2560

Modem I or O Machine 0.016-0.064

Network-LAN I or O Machine 100-1000

Graphics Display Output Human 800-8000

See Fig. 8.2 Text

buses in a pc connect a few devices

Memory bus

PCI:

Internal(Backplane)

I/O bus

CPU

SCSI:

External

I/O bus

PCI

Interface

Memory

Ethernet

Interface

SCSI

Interface

  • Data rates
    • Memory: 133 MHz, 8 bytes 1064 MB/s (peak)
    • PCI: 33 MHz, 8 bytes wide  264 MB/s (peak)
    • SCSI: “Ultra3” (80 MHz), “Wide” (2 bytes) 160 MB/s (peak)

(1 to 15 disks)

Ethernet Local

Area Network

Ethernet:

12.5 MB/s (peak)

Buses in a PC: connect a few devices
disk device terminology

Inner

Track

Outer

Track

Sector

Head

Arm

Platter

Actuator

Disk Device Terminology
  • Several platters, with information recorded magnetically on both surfaces (usually)
  • Bits recorded in tracks, which in turn divided into sectors (e.g., 512 Bytes)
  • Actuator moves head (end of arm,1/surface) over track (“seek”), select surface, wait for sector rotate under head, then read or write
    • “Cylinder”: all tracks under heads
disk device performance
Disk Device Performance

Inner

Track

Outer

Track

Sector

Head

Controller

Arm

Spindle

  • Disk Latency = Seek Time + Rotation Time + Transfer Time + Controller Overhead
  • Seek Time? depends no. tracks move arm, seek speed of disk
  • Rotation Time? depends on speed disk rotates, how far sector is from head
  • Transfer Time? depends on data rate (bandwidth) of disk (bit density), size of request

Platter

Actuator

disk device performance8
Disk Device Performance
  • Average distance sector from head?
  • 1/2 time of a rotation
    • 7200 Revolutions Per Minute  120 Rev/sec
    • 1 revolution = 1/120 sec  8.33 milliseconds
    • 1/2 rotation (revolution)  4.16 ms
  • Average no. tracks move arm?
    • Sum all possible seek distances from all possible tracks / # possible
      • Assumes average seek distance is random
    • Disk industry standard benchmark
disk performance model trends
Disk Performance Model /Trends
  • Capacity

+ 100%/year (2X / 1.0 yrs)

  • Transfer rate (BW)

+ 40%/year (2X / 2.0 yrs)

  • Rotation + Seek time

– 8%/ year (1/2 in 10 yrs)

  • MB/$

> 100%/year (2X / <1.5 yrs)

Fewer chips + areal density

disk performance
Disk Performance
  • Calculate time to read 1 sector (512B) for UltraStar 72 using advertised performance; sector is on outer track

Disk latency = average seek time + average rotational delay + transfer time + controller overhead

= 5.3 ms + 0.5 * 1/(10000 RPM) + 0.5 KB / (50 MB/s) + 0.15 ms

= 5.3 ms + 0.5 /(10000 RPM/(60000ms/M)) + 0.5 KB / (50 KB/ms) + 0.15 ms

= 5.3 + 3.0 + 0.10 + 0.15 ms = 8.55 ms

instruction set architecture for i o
Instruction Set Architecture for I/O
  • Some machines have special input and output instructions
  • Alternative model (used by MIPS):
    • Input: ~ reads a sequence of bytes
    • Output: ~ writes a sequence of bytes
  • Memory also a sequence of bytes, so use loads for input, stores for output
    • Called “Memory Mapped Input/Output”
    • A portion of the address space dedicated to communication paths to Input or Output devices (no memory there)
memory mapped i o

cmd reg.

data reg.

Memory Mapped I/O
  • Certain addresses are not regular memory
  • Instead, they correspond to registers in I/O devices

address

0

0xFFFF0000

0xFFFFFFFF

processor i o speed mismatch
Processor-I/O Speed Mismatch
  • 500 MHz microprocessor can execute 500 million load or store instructions per second, or 2,000,000 KB/s data rate
    • I/O devices from 0.01 KB/s to 30,000 KB/s
  • Input: device may not be ready to send data as fast as the processor loads it
    • Also, might be waiting for human to act
  • Output: device may not be ready to accept data as fast as processor stores it
  • What to do?
processor checks status before acting polling
Processor Checks Status before Acting: Polling
  • Path to device generally has 2 registers:
    • 1 register says it’s OK to read/write (I/O ready), often called Control Register
    • 1 register that contains data, often called Data Register
  • Processor reads from Control Register in loop, waiting for device to set Ready bit in Control reg to say its OK (0  1)
  • Processor then loads from (input) or writes to (output) data register
    • Load from device/Store into Data Register resets Ready bit (1  0) of Control Register
cost of polling
Cost of Polling?
  • Assume for a processor with a 500-MHz clock it takes 400 clock cycles for a polling operation (call polling routine, accessing the device, and returning). Determine % of processor time for polling
    • Mouse: polled 30 times/sec so as not to miss user movement
    • Floppy disk: transfers data in 2-byte units and has a data rate of 50 KB/second. No data transfer can be missed.
    • Hard disk: transfers data in 16-byte chunks and can transfer at 8 MB/second. Again, no transfer can be missed.
processor time to poll mouse floppy
% Processor time to poll mouse, floppy
  • Mouse Polling Clocks/sec

= 30 * 400 = 12000 clocks/sec

% Processor for polling = 12*103/500*106 = 0.002%  Polling mouse little impact on processor

  • Times Polling Floppy/sec

= 50 KB/s /2B = 25K polls/sec

Floppy Polling Clocks/sec

= 25K * 400 = 10,000,000 clocks/sec

% Processor for polling = 10*106/500*106 = 2%

 OK if not too many I/O devices

processor time to hard disk
% Processor time to hard disk
  • Times Polling Disk/sec

= 8 MB/s /16B = 500K polls/sec

Disk Polling Clocks/sec

= 500K * 400 = 200,000,000 clocks/sec

% Processor for polling:

200*106/500*106 = 40%

 Unacceptable

what is the alternative to polling interrupt
What is the alternative to polling? Interrupt
  • Wasteful to have processor spend most of its time “spin-waiting” for I/O to be ready
  • Wish we could have an unplanned procedure call that would be invoked only when I/O device is ready
  • Solution: use exception mechanism to help I/O. Interrupt program when I/O ready, return when done with data transfer
interrupt driven data transfer

(1) I/O

interrupt

Memory

add

sub

and

or

(2) save PC

user

program

(3) interrupt

service addr

(4)

read

store

...

jr

interrupt

service

routine

(5)

Interrupt Driven Data Transfer
benefit of interrupt driven i o
Benefit of Interrupt-Driven I/O
  • 500 clock cycle overhead for each transfer, including interrupt. Find the % of processor consumed if the hard disk is only active 5% of the time.
  • Interrupt rate = polling rate
    • Disk Interrupts/sec = 8 MB/s /16B = 500K interrupts/sec
    • Disk Polling Clocks/sec = 500K * 500 = 250,000,000 clocks/sec
    • % Processor for during transfer: 250*106/500*106= 50%
  • Disk active 5%  5% * 50%  2.5% busy
4 responsibilities leading to os
4 Responsibilities leading to OS
  • The I/O system is shared by multiple programs using the processor
  • Low-level control of I/O device is complex because requires managing a set of concurrent events and because requirements for correct device control are often very detailed
  • I/O systems often use interrupts to communicate information about I/O operations
  • Would like I/O services for all user programs under safe control
direct memory access dma
Direct Memory Access (DMA)
  • How to transfer data between a Device and Memory? Wastage of CPU cycles if done through CPU.
  • Let the device controller transfer data directly to and from memory => DMA
  • The CPU sets up the DMA transfer by supplying the type of operation, memory address and number of bytes to be transferred.
  • The DMA controller contacts the bus directly, provides memory address and transfers the data
  • Once the DMA transfer is complete, the controller interrupts the CPU to inform completion.
  • Cycle Stealing – Bus gives priority to DMA controller thus stealing cycles from the CPU
why networks
Why Networks?
  • Originally sharing I/O devices between computers (e.g., printers)
  • Then Communicating between computers (e.g, file transfer protocol)
  • Then Communicating between people (e.g., email)
  • Then Communicating between networks of computers  Internet, WWW
what makes networks work

Computer

switch

switch

switch

network

interface

What makes networks work?
  • links connecting switches to each other and to computers or devices
  • ability to name the components and to route packets of information - messages - from a source to a destination
  • Layering, protocols, and encapsulation as means of abstraction
typical types of networks
Typical Types of Networks
  • Local Area Network (Ethernet)
    • Inside a building: Up to 1 km
    • (peak) Data Rate: 10 Mbits/sec, 100 Mbits /sec,1000 Mbits/sec (1.25, 12.5, 125 MBytes/s)
    • Run, installed by network administrators
  • Wide Area Network
    • Across a continent (10km to 10000 km)
    • (peak) Data Rate: 1.5 Mbits/sec to 2500 Mbits/sec
    • Run, installed by telephone companies
  • Wireless Networks, ...
abcs many computers

appln

appln

OS

OS

network

interface

device

ABCs: many computers
  • switches and routers interpret the header in order to deliver the packet
  • source encodes and destination decodes content of the payload