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ECE 444 Session 5 Dr. John G. Weber KL-241E 229-3182 [email protected] [email protected] http://academic.udayton.edu/JohnWeber Combinatorial Logic Blocks Multiplexers Used to steer data

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Ece 444 l.jpg

ECE 444

Session 5

Dr. John G. Weber

KL-241E

229-3182

[email protected]

[email protected]

http://academic.udayton.edu/JohnWeber


Combinatorial logic blocks l.jpg
Combinatorial Logic Blocks

  • Multiplexers

    • Used to steer data

    • Suppose we want the output of a circuit, D, to be equal to the input A if a select signal is false and equal to the input B if the select signal is true

    • This circuit is a two-input, one-bit multiplexer which steers the data to the D input of a flip-flop


Verilog for 2 input mux l.jpg
Verilog for 2-input mux

//mux_2in_1b.v

//a two input, one-bit mux

module mux_2in_1b(d, a, b, sel);

input a, b, sel;

output d;

assign d = a && !sel || b && sel;

endmodule


Multiplexers l.jpg
Multiplexers

  • Extend this to a two-input, n-bit multiplexer


Verilog for n bit mux l.jpg
Verilog for n-bit mux

//mux_2in_nb.v

//parameterized, n-bit mux

module mux_2in_nb(D, A, B, sel);

parameter width =4;

input [width-1:0] A, B;

input sel;

output [width-1:0] D;

reg [width-1:0] D;

always @(sel or A or B)

if (sel) D = B;

else D = A;

endmodule


Behavioral modeling styles l.jpg
Behavioral Modeling Styles

  • Continuous Assignment Models

    • Used in the full-adder

  • Data Flow Models

    • Concurrent continuous assignment or asynchronous cyclic behavior

  • Algorithm Based Models

    • Abstract Model of behavior


Continuous assignment model l.jpg
Continuous Assignment Model

  • Consider a Simple Comparator

    • compares two vectors and returns A.lt.B, A.gt. B, or A = B

  • Verilog

  • //compare_4.v

  • //4-bit comparator

  • module compare_4(A_lt_B, A_gt_B, A_eq_B, A, B);

    • input [3:0] A, B;

    • output A_lt_B, A_gt_B, A_eq_B;

    • assign A_lt_B = (A < B);

    • assign A_gt_B = (A > B);

    • assign A_eq_B = (A == B);

  • endmodule


Parameterized compare module l.jpg
Parameterized Compare Module

  • Since the logic does not depend on the size of the vectors being compared, we can easily convert this to a parameterized module.

  • //compare_param_16.v

  • //16-bit parameterized comparator

  • module compare_param_16 (A_lt_B, A_gt_B, A_eq_B, A, B);

    • parameter width = 16

    • input [width-1:0] A, B;

    • output A_lt_B, A_gt_B, A_eq_B;

    • assign A_lt_B = (A < B);

    • assign A_gt_B = (A > B);

    • assign A_eq_B = (A == B);

  • endmodule


Data flow model l.jpg
Data Flow Model

  • Model with cyclic behavior

  • Use always construct

  • //compare_4.v

  • //4-bit comparator

  • module compare_4(A_lt_B, A_gt_B, A_eq_B, A, B);

    • input [3:0] A, B;

    • output A_lt_B, A_gt_B, A_eq_B;

    • [email protected](A or B)

      • begin

        • A_lt_B = (A < B);

        • A_gt_B = (A > B);

        • A_eq_B = (A == B);

      • end

  • endmodule

Note: Procedural assignment operator, =, is called a blocking

assignment and statements are executed in order.


Data flow model cont l.jpg
Data Flow Model (Cont.)

  • Consider a 4-bit shift register (see fig 5-7)

  • Flip-flops labeled (left to right) D, C, B, A

  • Verilog Code

  • //shiftright_4.v

  • module shiftright_4(E, D, C, B, A, clk, rst);

    • output A;

    • input E, clk, rst;

    • reg A, B, C, D;

    • always @(posedge clk or posedge rst)

      • begin

        • if (rst) begin A = 0; B = 0; C = 0; D = 0; end

        • else begin

          • A = B;

          • B = C;

          • C = D;

          • D = E;

          • end

      • end

    • endmodule

Blocking assignment


Data flow model cont11 l.jpg
Data Flow Model (Cont.)

  • To see effect of blocking assignment, reverse order of register assignment statements

  • //shiftright_4.v

  • module shiftright_4(E, D, C, B, A, clk, rst);

    • output A;

    • input E, clk, rst;

    • reg A, B, C, D;

    • always @(posedge clk or posedge rst)

      • begin

        • if (rst) begin A = 0; B = 0; C = 0; D = 0; end

        • else begin

          • D = E; //A = B;

          • C = D; //B = C;

          • B = C; //C = D;

          • A = B; //D = E;

          • end

      • end

    • endmodule

Blocking assignment causes D to have contents of E, then C to receive contents of D, then B to receive contents of C and finally A to receive contents of B on the same clock edge.

Degenerates into a single bit register.


Non blocking assignment l.jpg
Non-Blocking Assignment

  • Non-blocking assignment all assignment statements execute concurrently

  • Use non-blocking assignment operator <=

  • //shiftright_4.v

  • module shiftright_4(E, D, C, B, A, clk, rst);

    • output A;

    • input E, clk, rst;

    • reg A, B, C, D;

    • always @(posedge clk or posedge rst)

      • begin

        • if (rst) begin A = 0; B = 0; C = 0; D = 0; end

        • else begin

          • D <= E; //A <= B;

          • C <= D; //B <= C;

          • B <= C; //C <= D;

          • A <= B; //D <= E;

          • end

      • end

    • endmodule

Either order is fine and results in the desired 4-bit shift register


Algorithm based model l.jpg
Algorithm Based-Model

  • Describes function of module using an algorithm

  • Looks more like software but beware

  • //compare_algo_4.v

  • //4-bit comparator using an algorithm

  • module compare_algo_4(A_lt_B, A_gt_B, A_eq_B, A, B);

    • input [3:0] A, B;

    • output A_lt_B, A_gt_B, A_eq_B;

    • reg A_lt_B, A_gt_B, A_eq_B;

    • [email protected](A or B)

      • begin

        • A_lt_B = 0 //initialize outputs

        • A_gt_B = 0

        • A_eq_B = 0

        • if (A ==B) A_eq_B = 1;

        • else if (A > B) A_gt_B = 1;

        • else A_lt_B = 1;

      • end

  • endmodule


Sequential circuits l.jpg
Sequential Circuits

  • Use language features discussed last time to design sequential circuits

  • Discuss each feature as we use it in a series of examples

  • Sequential Circuit Block Diagram

  • Memory used to track the state of the circuit

  • Combinatorial logic used to determine next state as a function of inputs and current state

  • Combinatorial logic also used to derive output functions


Classical tools for sequential circuit design l.jpg
Classical Tools for Sequential Circuit Design

  • State Diagram

    • Provides a diagram of the available states, the conditions for switching states and the output at each state

  • State Table

    • Provides a tabular (truth table like) view of the states and the logic required

  • Algorithmic-State Machine (ASM) Charts (Ch 5 in text)

    • Flow chart type of presentation for finite state machines

  • Register Transfer Language

    • Provides a sequential language description of the inputs, outputs and next state requirement


Example sequential circuit requirement l.jpg
Example Sequential Circuit Requirement

  • Problem

    • Design a circuit that monitors a serial input and detects a string of three or more contiguous “ones”. When three or more “ones are detected in a row, generate a “one” on the output line.



State table l.jpg

Present State

Input

Next State

Output

A

B

x

A

B

y

0

0

0

0

0

0

0

0

1

0

1

0

0

1

0

0

0

0

0

1

1

1

0

0

1

0

0

0

0

0

1

0

1

1

1

0

1

1

0

0

0

1

1

1

1

1

1

1

State Table



Register transfer language l.jpg

State

Output

Next State

0

y  0

(x,!x)/(1,0)

1

y  0

(x,!x)/(2,0)

2

y  0

(x,!x)/(3,0)

3

y  1

(x,!x)/(3,0)

Register Transfer Language


Verilog hdl l.jpg
Verilog HDL

//seq_detect.v

//sample sequential machine to detect a sequence of three ones in a serial

//bit stream.

module seq_detect (x, y, clk, rst, state);

input x, clk, rst;

output y;

output [1:0] state;

reg y;

reg [1:0] state;

parameter S0 = 2'b00, S1 = 2'b01, S2 =2'b10, S3 = 2'b11;


Verilog hdl cont l.jpg
Verilog HDL(cont)

always @ (posedge clk or negedge rst)

if (~rst) begin

state = S0;

y=0;

end

else

case (state)

S0: begin y = 0; if(x) state = S1; else state = S0; end S1: if(x) state = S2; else state = S0;

S2: if(x) state = S3; else state = S0;

S3: begin

y = 1;

if(x) state = S3;

else state = S0;

endendcase

endmodule



Finite state machine types l.jpg
Finite State Machine Types

  • Two types—Mealy and Moore

  • Which was the Example?


Assignment 3 due wednesday 9 15 2004 l.jpg
Assignment 3 – Due Wednesday 9/15/2004

  • Goal

    • Practice in Verilog continuous and procedural assignments

    • Practice in Verilog module design.

  • Problems

    • Include a design specification and a structure description for each problem

    • Develop a verilog module and simulation for each problem

  • Design a 4-bit encoder

  • Design a 4-input priority encoder

  • Design a 8-input majority function (output is one if five or more inputs are asserted

  • Problem 1—page 100

  • Problem 2 – page 101


Project 1 due 2 october 2004 l.jpg
Project 1– Due 2 October 2004

  • Goal

    • Develop and demonstrate good design discipline and technique

    • Practice design of combinatorial logic circuits using Verilog HDL

  • Project

    • Develop 8-bit, two’s complement arithmetic ALU with data inputs A[7:0] and B[7:0] which performs the following operations asynchronously:

      • A + B

      • A – B

      • B – A

      • A OR B

      • A AND B

      • A XOR B

      • NOT A

      • NOT B

      • - A

      • - B

        For each function above, provide the following outputs

      • A > B

      • A < B

      • A = B

    • Timing Requirements: Maximum propagation delay for any function shall be less than 25 ns.

    • Provide a specification for each module, a structure write-up, a test plan, and a report describing your approach, results and conclusions


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