The Inclusive FVTX aka iFVTX sponsored by LANL-DR in FY ‘06-08 - PowerPoint PPT Presentation

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The Inclusive FVTX aka iFVTX sponsored by LANL-DR in FY ‘06-08 PowerPoint Presentation
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The Inclusive FVTX aka iFVTX sponsored by LANL-DR in FY ‘06-08
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The Inclusive FVTX aka iFVTX sponsored by LANL-DR in FY ‘06-08

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  1. The Inclusive FVTX aka iFVTX sponsored by LANL-DR in FY ‘06-08 • Chart • Business Model • Collaboration Roles • Thermal Issues • Readout • FNAL News • WBS

  2. Chart Mechanic Liaison Walt Sondheim Principal Investigator Pat McGaughey Deputy Project Leader TBA Co-PI/ ProjectLeader Gerd J. Kunde Co-PI/Theory Emil Mottola NoDCM Readout Dave Winter Sensors Jon Kapustinsky FPIX 2.1 Chips Gary Grim Cooling System Hytec Fast Readout M.Brooks Mark Prokop Calibration Pat McGaughey Thermal Management Hytec/CM. Lei Mechanics –Alignment Dave Lee, Hytec Module Assembly Dave Christian Testcard/Plane Procurement Guilherme Cardoso SlowControl Monitoring Hubert V. Hecke Module/Plane QA Gary Grim Plane/Station Assembly Dave Christian Enclosure Procurement FNAL ? LV/HV Gerd J. Kunde PHENIX Relations Gerd J. Kunde/Brian Cole

  3. Decisions and Collaboration • All decision are made after intensive discussion with all collaborators by an unanimous agreement between the PI, the project leader and the deputy project leader • Expert input will be especially valued to not engage in mirco-managing • The spirit of the work is a collaboration between the three involved institutions with a uniform appearance to the outside, especially PHENIX • Bi-Monthly collaboration meetings with rotating locations will be held with an agenda published well in advance • The meetings will include working sessions not just presentations • Weekly phone meetings will be conducted, with minutes to be posted • Information on the web will be essential and up to date

  4. Columbia Roles • NoDCM Clockless Readout (20 micro seconds) • According to Sergey an average 1 hit per central event with a 2.5 GHz fiber for each plane takes ~ 1.5 micro seconds to be received at the event builder • Test/Assembly work at FNAL • PHENIX Relations • Brian Cole and Bill Zajc • Personnel • Brian Cole (Bill Zajc) • Dave Winter • 2 Grad Students • 1 Undergrad

  5. FNAL Roles • MOU (to be modified with EE) • Test stands and pixel planes • New: test, pre-production, production • Guilherme is willing to contribute up to completion of project • MOU with EPP • Test Environment • Fixturing • Assembly (LAB 3) • Module Production • Plane Assembly • Thermal Management • Station Assembly

  6. LANL/Columbia Readout • DCM requirement (LANL Model) • LDRD and FVTX • 20 microsecond requirement, clockless (Columbia Model) • LDRD • FVTX • ‘Slow’ plus • Add additional path for level I to be developed later • Expert review in 2nd half of October, one from PHENIX, one completely independent

  7. Thermal Management • Proposed Division Line between FNAL and Hytec work • The half cylinder mounting structure • Manifold at the end of the cylinder • i.e. all plane related FEA and R&D done at FNAL • i.e. all overall management/design done by HYTEC • Material budget and distribution from FNAL • Temperature and Flow requirements from FNAL • Stability and Deformation • System Integration • Cylinder Shell Design (Production at FNAL?) • Starting point: HDI at room temperature

  8. FNAL Module News • First 8 chip module on the bench • No conclusive statements yet, ongoing work • The assembly was for lack of facilities not pre-tested before hybridization, i.e. not KGD or NGS • An 80 percent yield means 5 percent chance that all chips are working • Current module has 1 bad chip and unknown sensor • Frontend oscillations could cause the observed high current • Working points for all chips are not established yet • Analog debugging really important • Add analog lines to the HDI ? • To early to say whether there are problems, little steps at a time, it is not yet a proven system but R&D

  9. HDI Development • Current CERN HDI • Known compromises • Capacitor and resistor positions • Complexity to have 6 lines • No analog assessment • Only vendor is CERN • Sideline: CERN damaged the second batch, 18 out of 25 HDIs by drilling vias with the wrong size tool. Reproduction will be starting on October 2nd, • 4 month behind original assumptions • Kiss HDI • Development with ILC money for FNAL test beam • 1 readout line • Got hit line • Analog line • Clockless • Much simpler, including US vendors • Decision after more tests on which way to go • Balance risk with functionality

  10. Picture Plane Idea: picture plane & pixel module interface (LV and calibration) • CERN HDI plane • System test, as early as possible, 1 line sufficient • Clocks ? • passive • Pre production plane • Kiss HDI or CERN HDI • Will then determine the number of lines and readout • Passive • Production plane • Could be active with fiber driver, risk ? Could still have the serializer in rack on platform !

  11. Project Overview

  12. Integration

  13. Mechanics I

  14. Mechanics II

  15. Mechanics III

  16. Electronics Overview

  17. Sensors and Chips

  18. Pixel Module Interface

  19. HDI Schedules

  20. Pixel Planes

  21. Testcards

  22. LANL Readout

  23. Details not yet in the WBS To do list: • 1 – Select good 8-chip sensors to assemble onto next HDIs (Dave) • 2 – For the system at BNL:        • - Power supplies • - Pulse inject • 3 – Grounding and cooling (electrical connection between GND plane and TPG) • 4 – Talk to Tammy about wire bonding to the pixel plane Test facilities: • 1 – Set up new test stand at WH14 – Marcos, Ryan, Gingu • 2 – 2nd test stand at FCC3 using probe station computer – to be ready sometime in November for LANL and Columbia people • 3 – Test stand at LAB3 – December or later Tests to be completed • 1 – Decoupling capacitor tests. Do we need caps near the chips? Can we make the HDI wider by ~1mm? • 2 – Pixel module stability tests: RefRes, bypass of VRef (up or down), PS regulation requirements, grounding, needs to buffer analog output

  24. Discussion I • Walt reiterated the needs of input to HYTEC so that they can do mechancial studies: --full materials specifications for all pieces of the system --power-->heat generation:  amount and locations for the front end as well as readout electronics --alignment requirements --expectations for cable plant (number, shape, size), routing

  25. Discussion II • Discussion of what mechanical issues need to be tested with real systems or mock-ups.  Some various comments: --many tests should likely be done on 8-chip module alone (sensor+chips+HDI), including thermal cycling, testing of different possible adhesives, etc. --Not clear what mechanical/cooling tests exactly are rquired of a full plane. Walt promises to work on giving some input on this --Could likely do many tests with a mock-up which puts the correct heat loads in the correct places without actually using full 8-chip modules. --some more study should be done of what the optimal layout of a full station should be to minimize thermal issues:  should half-planes be oriented relative to each other in such a way that many thermal issues are effectively cancelled out?, again question of what is the correct adhesive to use?, more studies of the options of materials and cooling channels should be performed... --Not clear (to me) if you wanted to do mechanical and cooling tests if testing a 1/2 plane would be sufficient or if 2 full half-planes should really be tested --Little information known on what exactly could be populated in the proposed half-plane though it seems to be known that it could definitely _not_ have the full layup of sensor-chip-HDI over all or even most of the plane.  This information is needed to understand how limited the testing would be since we would not be testing exactly a plane as we would have in the real experiment. --overall it seemed more study, using models and testing individual 8-chip modules  before a mechanical prototype is produced would be prudent

  26. Discussion III • SCHEDULE: --WBS should have some real work put into it before schedule constraints are given --If we are to look at past schedule, including the delay of sensor, chip, HDI orders, it does not appear that the picture frame is either on the critical path or needed to go into production for several months at least.  But this should be established or not after (1) --Mark gave some estimates of DAQ development path, with the caveats that he has not tried to factor in resource availability.  Suggested milestones were: Electronics system interfaces defined    12/06 Electronics conceptual design complete    12/06 Prototype ROC/FEM available        04/07 DCM, GTM and support DAQ ready        04/07 System integration w/ 8 chip module    05/07 System testing                07/07 Redesigned ROC/FEM            10/07 Integration with Picture Frame        11/07 Testing w/ Picture Frame        03/08 From this, you would not need any picture frame to be available for testing before 04/07 at the earliest, and most likely would look for it a little later after the prototype ROC/FEMs are rung out. Need very clear input from FNAL on constraints of engineering availability for picture frame, especially since different answers were given to the question about constraints at different times during the silicon meeting.

  27. Discussion IV • ELECTRONICS: Various input on ideas of what electrical tests of the system are critical to producing a working system: --Would be very good to get at least a single 8-chip module into the PHENIX environment and DAQ ASAP.  There is enough uncertainty about what real hit rates will be, what event-by-event issues without Lvl-1 might be, what noise levels we might expect in a real system, etc. that any module taking some data prior to final installation and even final board production is expected to be highly valuable. --Certainly we will want to do cosmic ray tests, at least, early on before production.  Should we do a beam test somewhere as well? --Electrical tests before production must include: expected power sources, regulation, filtering same connectors and cabling as expected in real system full set of lines that will be used or desired in final system everything running at full clock speeds full data rate, as expected in the IR, tested

  28. Discussion V • Some open technical questions on proposed prototype board: --Why would we sacrifice bringing another data line per chip out for getting the chip_hit out, which is only useful as feed-in to Lvl-1 (which we can't do without more data lines)? --Not clear that having no clock provided is a technically simpler solution than bringing a clock out:  if you over-sample then there are issues with the rate at which the FPGA has to run..., if you try to use the clock sent down also for the read-back there are likely resource and other issues with synching up a number of different chips which will likley have had different delays... --In addition to ruling out the possibility of participating in Lvl-1, a single data line per chip may additionally lock us into a corner if we have noise levels eve at the level of 0.01% as it only takes 1/2 noise hit per chip to fill the data stream just with noise if we have only one data line coming out.  Is this a good trade-off against the technical challenges of bringing multiple data lines to our connectors? Sergey also presented a very nice tabular summary of data through-put if you different numbers of data lines, serdes, DCM channels... I will add his table to the page of electronics documents.