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Advanced_MOSFET

A brief description with schematic structures of various advanced MOSFET architectures

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Advanced_MOSFET

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  1. Course: Nanoelectronic Device Arpan Deyasi Nanoelectronic Advanced MOSFET Architectures Device Arpan Deyasi RCCIIT, Kolkata 19-06-2021 Arpan Deyasi, RCCIIT, India 1

  2. Problems in Bulk MOSFET while downsizing Arpan Deyasi G Dielectric channel D D S S Excessive short-channel effects Nanoelectronic substrate substrate Minimum channel length becomes 50 nm approx., can’t be reduced further Device Lower threshold for Gate oxide scaling Lower threshold for Supply voltage Discrete dopant fluctuations 19-06-2021 Arpan Deyasi, RCCIIT, India 2

  3. Possible Solutions Better gate control to nullify the short channel effect Arpan Deyasi Incorporation of high-K dielectric to reduce tunneling effect, which simultaneously helps to reduce dielectric thickness Nanoelectronic Use of semiconductors with higher carrier mobility as substrate material Device 19-06-2021 Arpan Deyasi, RCCIIT, India 3

  4. Better gate control Better scalability and lower sub threshold current Arpan Deyasi Novel architectures are proposed for the purpose Nanoelectronic Device Gate Multi-gate architecture SOI with multi-gate wrapping 19-06-2021 Arpan Deyasi, RCCIIT, India 4

  5. Multi-gate Architecture First design is Double-Gate MOSFET Arpan Deyasi Nanoelectronic Top Gate Device Top Dielectric Channel Drain Drain Source Source Bottom Dielectric Bottom Gate 19-06-2021 Arpan Deyasi, RCCIIT, India 5

  6. Double-Gate MOSFET Arpan Deyasi Nanoelectronic Drain Device Gate Gate Source 19-06-2021 Arpan Deyasi, RCCIIT, India 6

  7. Double Gate MOSFET Front and back gates control carrier flow in channel region Arpan Deyasi Channel length is scalable upto 30 nm Nanoelectronic Ultrathin channel works as quantum confined region Device ION/IOFFratio is better compared with single gate MOSFET Lower subthresholdslope Lower gate leakage 19-06-2021 Arpan Deyasi, RCCIIT, India 7

  8. Drawbacks of Double Gate MOSFET Arpan Deyasi Electric field between body and drain increases band-to-band tunneling probability Nanoelectronic Small channel length provides reduced potential width, which leads to quantum mechanical tunneling between source and drain Device Owing to lower potential barrier, thermionic emission takes place Quantum confinement effect in ultrathin body region 19-06-2021 Arpan Deyasi, RCCIIT, India 8

  9. Tri-Gate MOSFET Arpan Deyasi Nanoelectronic Drain Gate Device Gate Gate Source 19-06-2021 Arpan Deyasi, RCCIIT, India 9

  10. Tri-Gate MOSFET Conducting channel forms across all three sides, two on sides, one at top Arpan Deyasi Nanoelectronic Additional control enables maximum possible current flow at ON state, makes close to zero when OFF state, and helps the device to switch as quick as possible between the two states Device 19-06-2021 Arpan Deyasi, RCCIIT, India 10

  11. Advantages of Tri-Gate MOSFET Arpan Deyasi Performance gain at lower operating voltage Nanoelectronic Low power operation speaks for power reduction Device Higher drive current Improved switching characteristics 19-06-2021 Arpan Deyasi, RCCIIT, India 11

  12. Disadvantages of Tri-Gate MOSFET Arpan Deyasi Conventional fabrication technology makes hindrance for non-planar growth Nanoelectronic Fabrication of semiconductor ‘fin’ of nano-dimension Device Fabrication of matched gates on multiple sides of ‘fin’ 19-06-2021 Arpan Deyasi, RCCIIT, India 12

  13. Quadruple-Gate MOSFET Arpan Deyasi Nanoelectronic Drain Gate Device Gate Gate Source Gate 19-06-2021 Arpan Deyasi, RCCIIT, India 13

  14. Quadruple-Gate MOSFET Better gate control …………… Arpan Deyasi Problem is related to fabrication …………… Nanoelectronic Therefore, alternative architecture is considered having same effect …………… Device Gives birth to Gate-All-Around Architecture 19-06-2021 Arpan Deyasi, RCCIIT, India 14

  15. GAA MOSFET Arpan Deyasi Nanoelectronic source Device gate drain channel 19-06-2021 Arpan Deyasi, RCCIIT, India 15

  16. Advantages of GAA MOSFET Better gate controllability as gate is all around the channel Arpan Deyasi Leakage current is almost negligible Nanoelectronic Short channel effect is negligible Device Higher drain current Lower Subthreshold slope 19-06-2021 Arpan Deyasi, RCCIIT, India 16

  17. SOI Technology Si channel layer is grown on oxide layer Arpan Deyasi Negligible junction capacitance Nanoelectronic Electrical active layer is isolated from bulk layer Low leakage current Device Reduced parasitic effect Superior electrostatic control 19-06-2021 Arpan Deyasi, RCCIIT, India 17

  18. SOI MOSFET Arpan Deyasi MOSFET device in which a semiconductor layer is formed on an insulator layer which may be a buried oxide (BOX) layer formed in a semiconductor substrate Nanoelectronic Why it is on demand? Allows continuous miniaturization of MOSFET Device Low parasitic resistances and capacitances Compatible with existing fabrication techniques Providing higher current densities 19-06-2021 Arpan Deyasi, RCCIIT, India 18

  19. SOI MOSFET structure gate Arpan Deyasi gate drain source Nanoelectronic source drain gate dielectric gate dielectric Device n+ p BOX n+ n+ n+ p-body p-body 19-06-2021 Arpan Deyasi, RCCIIT, India 19

  20. Different SOI MOSFET Arpan Deyasi Partially depleted MOSFET Thickness of p-region (sandwiched between gate oxide and buried oxide) is greater than bulk depletion width KINK effect is observed Nanoelectronic Fully depleted MOSFET Si film thickness is less than bulk depletion width No such effect is observed Device Comparatively slower Comparatively faster Behaves like bulk MOSFET Doesn’t behave like bulk MOSFET Used in analog circuit Used in low power applications Drawback: packaging scalability Drawback: complex fabrication process 19-06-2021 Arpan Deyasi, RCCIIT, India 20

  21. Partially depleted MOSFET Fully depleted MOSFET Front-gate Arpan Deyasi Front-gate Nanoelectronic drain source drain source Body Device Back-gate Back-gate 19-06-2021 Arpan Deyasi, RCCIIT, India 21

  22. Advantages of SOI MOSFET Lower parasitic capacitance due to isolation from semiconductor substrate, which improves power conservation Arpan Deyasi Resistance to latch-up due to complete isolation of n-well and p-well structures Nanoelectronic Lower leakage currents Device Reduced temperature dependency Steeper sub-threshold swing 19-06-2021 Arpan Deyasi, RCCIIT, India 22

  23. Disadvantages of SOI MOSFET Kink effect Arpan Deyasi Self-heating effect Nanoelectronic Floating body effect can get freely charged/ discharged due to transients which affects threshold voltage Device 19-06-2021 Arpan Deyasi, RCCIIT, India 23

  24. FinFET Arpan Deyasi Nanoelectronic Drain Gate Device Gate Gate Source 19-06-2021 Arpan Deyasi, RCCIIT, India 24

  25. FinFET characteristics Non-planar DGMOSFET built on SOI substrate Arpan Deyasi Conducting channel is wrapped up by Si thin ‘fin’ which forms body of the device Nanoelectronic Thickness of ‘fin’ determines effective channel length of device Device It is basically vertical Double Gate MOSFET 19-06-2021 Arpan Deyasi, RCCIIT, India 25

  26. Advantages of FinFET Suppressed short channel effect Arpan Deyasi Higher driving current Nanoelectronic Higher technological maturity than planar DGMOSFET Device More compact in terms of architecture Lower cost 19-06-2021 Arpan Deyasi, RCCIIT, India 26

  27. Disadvantages of FinFET Reduced mobility for electrons Arpan Deyasi Higher source and drain resistances Nanoelectronic Poor reliability Device 19-06-2021 Arpan Deyasi, RCCIIT, India 27

  28. Direction towards low power electronics Arpan Deyasi Lower subthreshold swing Nanoelectronic Higher speed of operation Promising candidate for low power electronics Device Steeper subthreshold slope 19-06-2021 Arpan Deyasi, RCCIIT, India 28

  29. Tunnel FET Arpan Deyasi Gate Gate Nanoelectronic Source Drain Source Drain BOX Device p+ n+ n+ p+ n i BOX substrate substrate n-TFET p-TFET 19-06-2021 Arpan Deyasi, RCCIIT, India 29

  30. Tunnel FET characteristics Operation is based on principle of band-to-band tunneling Arpan Deyasi Switch between OFF and ON states at low voltages Nanoelectronic Uses gate-controlled p-i-n structure with carrier with carriers tunneling through barrier Device Interband tunneling occurs in heavily doped p+ - n+junctions Less amount of current compared with MOSFET 19-06-2021 Arpan Deyasi, RCCIIT, India 30

  31. Tunnel FET characteristics Very low leakage current at OFF state Arpan Deyasi Steeper subthreshold slope Nanoelectronic Higher ON-to-OFF current ratio Device 19-06-2021 Arpan Deyasi, RCCIIT, India 31

  32. TFET Band Diagram Arpan Deyasi ON Nanoelectronic ?? Device ?? OFF Drain Channel Source 19-06-2021 Arpan Deyasi, RCCIIT, India 32

  33. Electrical characteristics of TFET Arpan Deyasi OFF state: wider potential barrier restricts tunneling Nanoelectronic ON state: gate voltage exceeds threshold voltage which reduces potential barrier width, and therefore tunneling starts Device Channel valence band lifted above source conduction band which makes tunneling possible Only carriers in energy window ΔΦ can tunnel from source to channel 19-06-2021 Arpan Deyasi, RCCIIT, India 33

  34. Advantages of Tunnel FET Subthreshold slope lower than 60 mV/decade Arpan Deyasi Highest possible ON current and lowest possible OFF current Nanoelectronic Higher intrinsic voltage gain and higher maximum oscillation frequency at low current levels compared with FinFET Device 19-06-2021 Arpan Deyasi, RCCIIT, India 34

  35. Disadvantages of Tunnel FET Arpan Deyasi Magnitude of current is smaller than that of MOSFET Nanoelectronic Device 19-06-2021 Arpan Deyasi, RCCIIT, India 35

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