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第3章 计算机的基本器件. 下一页. 目 录. 3.1 逻辑代数与逻辑电路 3.2 组合逻辑电路 3.3 时序逻辑电路 3.4 总线缓冲器和总线控制器 3.5 时钟发生器. 上一页. 下一页. 3.1 逻辑代数与逻辑电路. 3.1.1 逻辑代数 3.1.2 基本逻辑电路. 上一页. 下一页. 3.1.1 逻辑代数.

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第3章 计算机的基本器件

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3


3.1

3.2

3.3

3.4

3.5


3.1

3.1.1

3.1.2


3.1.1

Boolean algebra


3.1.1

01


+ABC1F1ABC0F0

F ABCABC+

ABC


ABC1F10

F ABCABC

ABC


A10A01

F

A


3.1.1

F=f(A1,A2,,Ai,,An)


ABF10

F=f(A,B)=



3.1.1

F=A+B F=AVB


3.1.1

F=AB F=A B


3.1.1


3.1.1

P57P58


3.1.1




3.1.2


3.1.2


3.1.2


3.1.2



10

10


3.2


3.2

3.2.1

3.2.2

3.2.3

3.2.4


3.2.1

:AiBiCi


Si=AiBi

Ci= AiBi


Ci-1


SI=AIBICI-1CI=AIBI+BICI-1+AICI-1


3.n

4

n


3.2.2

ALUArithmetic Logic UnitALUALUALU


3.2.3


3.2.3

1.

3-838

3x2x1x08y7y6y5y4y3y2y1y0



3-8


74LS1383-8(a)(b)

G10G211


3.2.4

MUX (Multiplexor/Selector)


3.2.4

41MUX4ABCDZ()S1S0


3.3


3.3

3.3.1

3.3.2

3.3.3


3.3.1

(flip-flop)

-

R-SDJ-K


1.R-S

100R=0S=1QQ0

R=1 S=0Q Q1

R=1 S=1

R=0 S=0


2.R-S

R-SCPR-S

R0 S1CPQ(t)Q(t+1)


3.D

D

D

RD0SD1(RDSD)D()DD=11D=00


4.J-K

RD0SD1K0J1

J=0K=0CP

J=0K=1CP0

J=1K=0CP1

J=1K=1CP


3.3.2

nn


3.3.2

D4CP


CKQD


CP


74LS3738D8D


nnD

R0DRD Q1=Q2=Q3==Qn=0

DINCPDDIN =1CPFF1FF1CPD


DDDCPD

DQ

2()


3.3.3


3.3.3

1.

2.

3.


4

4:

DCPDQQCP


R0Q3Q2Q1Q00000CPQ01Q010CPQ00Q001Q11CPQ3Q2Q1Q00000



3.4

3.4.1

3.4.2


3.4.1

74LS24474LS245

74LS244 83-18

74LS245 83-19


3-18 74LS244


3-19 74LS245


3.4.2

8288

3-20 8288


3.5

3.5.1 8284

3.5.2 8284CPU


3.5.1 8284

828418


82845

1.OSC

2.CLKCLKCPU

3.RESETCPU

4.PCLKCLK2

5.READY8284RDY1AEN1RDY2AEN2ASYNC


3.5.2 8284CPU

PC/XT8284


PWR GOOD RRESET8088

DMA WAIT DMA()DMADMA()

RDY/WAITI/O CH RDYIORIOW8284READY


3 The End


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