Elec 7770 advanced vlsi design spring 2007 binary decision diagrams
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ELEC 7770 Advanced VLSI Design Spring 2007 Binary Decision Diagrams. Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 [email protected] http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07. Methods of Equivalence Checking.

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ELEC 7770 Advanced VLSI Design Spring 2007 Binary Decision Diagrams

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ELEC 7770Advanced VLSI DesignSpring 2007Binary Decision Diagrams

Vishwani D. Agrawal

James J. Danaher Professor

ECE Department, Auburn University

Auburn, AL 36849

[email protected]

http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07

ELEC 7770: Advanced VLSI Design (Agrawal)


Methods of Equivalence Checking

  • Satisfiability algorithms

  • ATPG methods

  • Binary decision diagrams (BDD)

ELEC 7770: Advanced VLSI Design (Agrawal)


Shannon’s Expansion Theorem

  • C. E. Shannon, “A Symbolic Analysis of Relay and Switching Circuits,” Trans. AIEE, vol. 57, pp. 713-723, 1938.

  • Consider:

    • Boolean variables, X1, X2, . . . , Xn

    • Boolean function, F(X1, X2, . . . , Xn)

  • Then F = Xi F(Xi=1) + Xi’ F(Xi=0)

  • Where

    • Xi’ is complement of Xi

    • Cofactors, F(Xi=j) = F(X1, X2, . . , Xi=j, . . , Xn), j = 0 or 1

  • ELEC 7770: Advanced VLSI Design (Agrawal)


    Theorem

    (1)F = Xi F(Xi=1) + Xi’ F(Xi=0)∀ i=1,2,3, . . . n

    (2)F = (Xi + F(Xi=0)) (Xi’ + F(Xi=1)) ∀ i=1,2,3, . . . n

    F(Xi=0) F(Xi=1)

    0 1

    Xi

    F

    ELEC 7770: Advanced VLSI Design (Agrawal)


    Expansion About Two Inputs

    • F = XiXj F(Xi=1, Xj=1) + XiXj’ F(Xi=1, Xj=0)

      + Xi’Xj F(Xi=0, Xj=1)

      + Xi’Xj’ F(Xi=0, Xj=0)

    • In general, a Boolean function can be expanded about any number of input variables.

    • Expansion about k variables will have 2k terms.

    ELEC 7770: Advanced VLSI Design (Agrawal)


    Binary Decision Tree

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    Graph representation

    of a Boolean function.

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    Leaf nodes

    ELEC 7770: Advanced VLSI Design (Agrawal)


    Binary Decision Diagrams

    • Binary decision diagram (BDD) is a graph representation of a Boolean function, directly derivable from Shannon’s expansion.

    • References:

      • C. Y. Lee, “Representation of Switching Circuits by Binary Decision Diagrams,” Bell Syst. Tech J., vol. 38, pp. 985-999, July 1959.

      • S. Akers, “Binary Decision Diagrams,” IEEE Trans. Computers, vol. C-27, no. 6, pp. 509-516, June 1978.

    • Ordered BDD (OBDD) and Reduced Order BDD (ROBDD).

    • Reference:

      • R. E. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation,” IEEE Trans. Computers, vol. C-35, no. 8, pp. 677-691, August 1986.

    ELEC 7770: Advanced VLSI Design (Agrawal)


    Binary Decision Diagram

    • BDD of an n-variable Boolean function is a tree:

      • Root node is any input variable.

      • All nodes in a level are labeled by the same input variable.

      • Each node has two outgoing edges, labeled as 0 and 1 indicating the state of the node variable.

      • Leaf nodes carry fixed 0 and 1 labels.

      • Levels from root to leaf nodes represent an ordering of input variables.

      • If we trace a path from the root to any leaf, the label of the leaf gives the value of the Boolean function when inputs are assigned the values from the path.

    ELEC 7770: Advanced VLSI Design (Agrawal)


    Ordered Binary Decision Diagram (OBDD)

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    OBDD

    Tree

    ELEC 7770: Advanced VLSI Design (Agrawal)


    OBDD With Different Input Ordering

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    ELEC 7770: Advanced VLSI Design (Agrawal)


    Evaluating Function from OBDD

    • Start at leaf nodes and work toward the root – leaf node functions are 0 and 1.

    • Function at a node with variable x is

      f = x’.f(low) + x.f(high)

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    ELEC 7770: Advanced VLSI Design (Agrawal)


    Cannot Compare Two Circuits

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    ELEC 7770: Advanced VLSI Design (Agrawal)


    OBDD Graph Isomorphism

    • Two OBDDs are isomorphic if there is one-to-one mapping between the vertex sets with respect to adjacency, labels and leaf values.

    • Two isomorphic OBDDs represent the same function.

    • Two identical circuits may not have identical OBDDs even when same variable ordering is used.

    • Comparison is possible if:

      • Same variable ordering is used.

      • Any redundancies in graphs are removed.

    ELEC 7770: Advanced VLSI Design (Agrawal)


    Reduced Order BDD (ROBDD)

    • Directed acyclic graph (DAG) (*).

    • Contains just two leaf nodes labeled 0 and 1.

    • Variables are indexed, 1, 2, . . . n, such that the index of a node is greater than that of its child (*).

    • A node has exactly two child nodes, low and high, that low ≠ high.

    • Graph contains no pair of nodes such that subgraphs rooted in them are isomorphic.

    * Properties common to OBDD.

    ELEC 7770: Advanced VLSI Design (Agrawal)


    ROBDDs

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    Isomorphic

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    ELEC 7770: Advanced VLSI Design (Agrawal)


    Reduction: OBDD to ROBDD

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    ELEC 7770: Advanced VLSI Design (Agrawal)


    Properties of ROBDD

    • Unique for given variable ordering – graph isomorphism verifies logic equivalence.

    • Size (number of nodes) changes with variable ordering – worst-case size is exponential (e.g., integer multiplier).

    • Other applications: logic synthesis, testing.

    • For algorithms to derive ROBDD, see

      • R. E. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation,” IEEE Trans. Computers, vol. C-35, no. 8, pp. 677-691, August 1986.

      • G. De Micheli, Synthesis and Optimization of Digital Circuits, New York: McGraw-Hill, 1994.

      • S. Devadas, A. Ghosh, and K. Keutzer, Logic Synthesis, New York: McGraw-Hill, 1994.

    ELEC 7770: Advanced VLSI Design (Agrawal)


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