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WRR ARBITER Characterization Presentation

WRR ARBITER Characterization Presentation. Students: Ofer Sobel Guy Marcus Supervisor: Moshe Porian. 16/11/10. Introduction. WRR algorithm arbitrates between clients, requesting usage of the same resource.

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WRR ARBITER Characterization Presentation

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  1. WRR ARBITERCharacterization Presentation Students: OferSobel Guy Marcus Supervisor: Moshe Porian 16/11/10

  2. Introduction • WRR algorithm arbitrates between clients, requesting usage of the same resource. • Arbitration is performed considering priority weights, assigned to each client. ARBITER

  3. Project Goal Implementing a WRR ARBITER on an FPGA • Implementation will be to Altera Cyclone® II 2C35 FPGA located on an Altera DE2 board • A simulation environment for the WRR arbiter to interact with will also be implemented.

  4. Specifications • Generic number of clients (1 to 4) • Communication with host via UART protocol • Real-Time configurable arbitration weights • Interaction with switches and LEDs • 60 MHZ system clock (generated from board’s 50MHz clock)

  5. Project steps • Determining specifications • Architecture characterization • Conceptual design • VHDL implementation • Verification • Synthesis • Real-Time testing

  6. Top level design

  7. Communication with host – UART Start bit = ‘0’ Data Parity Stop bit = ‘1’ Idle state: Constant marking (‘1’). Start bit: 1 bit of spacing (‘0’). Data: 5 to 8 data bits. Parity: optional parity bit of type ‘odd’ or ‘even’. Stop bit: 1 bit of marking (‘1’). Baud rate: 2400, 4800, 9600, 19200, 38400, 57600 or 115200 bits/sec ±3%

  8. Message Structure A packet of data is constructed in the following way (every block is 1 byte long): scope for CRC Start Address Start 0x00 End 0x15 Type Length Data(1) Data(n) CRC n is determined by ‘Length’ byte write: 0x00 read: 0x1F reply: 0x07 status: 0x18 x8+x7+x6+x4+x2+1

  9. RX path – data flow • Host sends message via RX line. • 2. Receiver packs incoming bits (UART protocol). • 3. Message-Decoder decodes sequences of bytes (message protocol). • Register-Bus-Master executes message according to type: • Writes data to the Register Bus/ Initiates reply message.

  10. TX path – data flow • Register-Bus-Master is signaled to initiate a message. • Register-Bus-Master loads data to the Message-Encoder and encoder FIFO. • Message-Encoder drives the Transmitter with bytes (message protocol). • Transmitter transmits message to the host via the TX line (UART protocol).

  11. Verification concept

  12. Verification concept (cont.)

  13. Simulation Environment • Simulation using input scripts and output logs • Error/warning tracking • Direct/ Random simulations • Golden model reference • Waves monitoring and recording

  14. GUI Demo

  15. Schedule

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