Reducing memory penalty by a programmable prefetch engine for on chip caches
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Reducing memory penalty by a programmable prefetch engine for on-chip caches. Presentatie voor het vak computerarchitectuur door Armin van der Togt. Indeling:. Probleemstelling De prefetch architectuur Resultaten Conclusies Gerelateerd werk. Probleemstelling.

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Reducing memory penalty by a programmable prefetch engine for on chip caches

Reducing memory penalty by a programmable prefetch engine for on-chip caches

Presentatie voor het vak computerarchitectuur door

Armin van der Togt


Indeling
Indeling: for on-chip caches

  • Probleemstelling

  • De prefetch architectuur

  • Resultaten

  • Conclusies

  • Gerelateerd werk


Probleemstelling
Probleemstelling for on-chip caches

  • Verschil tussen snelheid van geheugen en CPU wordt steeds groter dus: cache en prefetching

  • Hardware prefetching duur en complexe geheugen structuren moeilijk

  • Software prefetching veel executie overhead


Software prefetching

Original code for on-chip caches

Generated code

(inner loop only)

Software prefetching


De prefetch architectuur

Hare for on-chip caches

Prefetch

Engine

Firing

ALU

on-chip

cache

De prefetch architectuur

Run-Ahead Table

PC

ORQ

Memory

system

Processor chip


iaddr: for on-chip caches PC om prefetch te starten

<base, stride>: prefetch adres en stapgrootte

<count, start>: prefetch condities

count: eens in de count keer dat PC=iaddr wordt een prefetch gestart

start: pas na start keer dat aan de bovenstaande conditie is voldaan mag begonnen worden met prefetchen

Nieuwe instructie voor de prefetch engine:

fill_run_ahead iaddr, <base, stride> , <count, start>


Voorbeeld
Voorbeeld for on-chip caches


Code met prefetch instructies for on-chip caches

memory latency

=

5 cycles


Resultaten
Resultaten for on-chip caches


Conclusies
Conclusies for on-chip caches

  • Prefetching kan geheugen penalty tot 80% verlagen

  • Een programeerbare prefetch engine verlaagt de penalty ten opzichte van software prefetching

  • Bij kleine caches (1-2k) is de programmerbare prefetch engine relatief duur

  • de compiler moet prefetching ondersteunen


Gerelateerd werk
Gerelateerd werk for on-chip caches

  • Fu and Patel: stride directed prefetching in scalar processors (hardware)

  • Mowry and Gupta: software controlled prefetching

  • Chiueh: A programmable hardware prefetch architecture for numerical loops (lijkt hier op)


Literatuur
Literatuur for on-chip caches

  • Tien-Fu Chen, Reducing memory penalty by a programmable prefetch engine for on-chip caches, Microprocessors and Microsystems, 21 (1997) 121-130


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