Branch predictor interface
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Branch Predictor Interface. typedef struct { Bool taken; Addr target; } BPBundle deriving (Bits, Eq ); interface BPredictor ; method BPBundle prediction( Addr pc); method Action update( Addr pc, Addr target, IType type, Bool taken); endinterface. Null Branch Prediction.

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Branch Predictor Interface

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Branch predictor interface

Branch Predictor Interface

typedefstruct {

Bool taken;

Addr target;

}

BPBundlederiving(Bits, Eq);

interface BPredictor;

method BPBundle prediction(Addr pc);

method Action update(Addr pc,

Addr target,

IType type,

Bool taken);

endinterface

http://csg.csail.mit.edu/SNU


Null branch prediction

Null Branch Prediction

module mkNeverTaken(BPredictor);

method BPBundle prediction(Addr pc);

return BPBundle{taken: False,

target: pc+4};

method update = ?;

endmodule

  • Replaces PC+4 with …

    • Already implemented in the pipeline

  • Right most of the time

    • Why?

http://csg.csail.mit.edu/SNU


Two stage smips

Two-Stage SMIPS

Register File

Epoch

PC

Execute

Decode

fr

+4

Data

Memory

Inst

Memory

http://csg.csail.mit.edu/SNU


Two stage smips bp

Two-Stage SMIPS + BP

Register File

Epoch

PC

Execute

Decode

fr

Branch

Predictor

bpr

Data

Memory

Inst

Memory

http://csg.csail.mit.edu/SNU


Two stage smips bp1

Two-Stage SMIPS +BP

module mkProc(Proc);

Reg#(Addr) pc <- mkRegU;

Reg#(Bool) epoch <- mkRegU;

RFilerf <- mkRFile;

BranchPredictorbpred <- mkNeverTaken;

Memory mem <- mkTwoPortedMemory;

letiMem = mem.iport; letdMem = mem.dport;

PipeReg#(FBundle) fr <- mkPipeReg;

PipeReg#(BPBundle) bpr <- mkPipeReg;

http://csg.csail.mit.edu/SNU


Two stage smips bp2

Two-Stage SMIPS +BP

ruledoProc;

BPBundlebp = bpred(pc);

if(fr.notFull&& bp.notFull) begin

letinst <- iMem(MemReq{op: Ld, addr: pc,

data: ?});

fr.enq(FBundle{pc: pc, epoch: epoch,

inst: inst});

bpr.enq(bp);

end

http://csg.csail.mit.edu/SNU


Two stage smips bp3

Two-Stage SMIPS + BP

Addr redirPc = ?; Bool redirPCvalid = False;

if(fr.notEmpty) begin

let frpc = fr.first.pc;

let inst = fr.first.inst;

if(fr.first.epoch==epoch) begin

let dInst = decode(inst);

Data rVal1 = rf.rd1(dInst.rSrc1);

Data rVal2 = rf.rd2(dInst.rSrc2);

let eInst = exec(dInst, rVal1, rVal2, frpc);

if(memType(eInst.iType))

eInst.data <- dMem(MemReq{

op: eInst.iType==Ld ? Ld : St,

addr: eInst.addr, data: eInst.data});

http://csg.csail.mit.edu/SNU


Branch predictor interface

Two-Stage SMIPS +BP

if(eInst.brTaken) begin

redirPC = eInst.addr;

redirPCvalid= eInst.brTaken != bpr.brTaken;

end

bp.update(bpr.pc,eInst.addr,

eInst.iType, eInst.brTaken);

if(regWriteType(eInst.iType))

rf.wr(eInst.rDst, eInst.data);

end

fr.deq;

bpr.deq;

end1

pc <= redirPCvalid ? redirPC : bp.target;

epoch <= redirPCvalid? !epoch : epoch;

endruleendmodule

http://csg.csail.mit.edu/SNU


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