Signal and Timing Parameters II Source Synchronous Timing – Class 3

1. Signal and Timing Parameters IISource Synchronous Timing – Class 3 a.k.a. Co-transmitted Clock Timinga.k.a. Clock Forwarding. Assignment for next class: Download HSPICE manual from Intel Lab. Acknowledgements: Intel Bus Boot Camp: Howard Heck

2. Contents • Synchronous Bus Limitations • Source Synchronous Concept & Advantages • Operation • Timing Equations • Timing Loop Analysis • Maximum Transfer Rate • Beyond “Double Pumping” • Edge Considerations Signal Parameters & Timing Class 3

3. Common Clock Limitations • Max frequency is defined by min cycle time • Min cycle time is limited by maximum delays. • Can we find a way to remove the dependence on absolute delays? Signal Parameters & Timing Class 3

4. Source Synchronous Signaling Concept • The transmitting agent (A) sends the clock (“strobe”), along with the data signal. • A central clock is not (directly) required to control data flow from transmitter to receiver. • Overview: • Drive the strobe and data signals with a known phase relationship. • Design the strobe and data signals to be identical in order to preserve the phase relationship. • As long as the phase relationship can be maintained, the lines can be arbitrarily long (limited by other effects, such as losses, latencies, etc.). Signal Parameters & Timing Class 3

5. Source Synchronous Concept Example • Suppose that we transmit a data signal 1 ns prior to transmitting the strobe. • You’re given a 500 ps receiver setup requirement. • You find that the flight time for the data signal varies between 5.5 ns and 5.7 ns. • You find that the flight time for the strobe signal also varies between 5.5 ns and 5.7 ns, but the two signals are not correlated. • Can we meet the setup requirement? Signal Parameters & Timing Class 3

6. Source Synchronous Advantage • From the preceding example, it should be apparent that source synchronous performance depends on relative, rather than absolute delays. • True for drivers and interconnect, though we must still meet the absolute setup/hold requirements for the receiver. • In real systems, the difference in delay between signals can be made much smaller than the absolute delays. • Therefore, with source synchronous signaling we can expect • to achieve higher performance • to be able to use longer traces Signal Parameters & Timing Class 3

7. Transfer Rate Comparison Items in parentheses are in development, all others are released in products. Signal Parameters & Timing Class 3

8. Driver Chip From Core D Q D DELAY Strobe n n n From Core D Q P L Data L Clock Distribution Tree Data Receiver Chip To Core Q D Q D System n Clock Strobe P L L Clock Distribution Tree Source Synchronous Bus Operation Signal Parameters & Timing Class 3

9. Driver Chip From Core D Q D DELAY n Strobe n n From Core D Q P L Data L Clock Distribution Tree Data Receiver Chip To Core Q D Q D System n Clock Strobe P L L Clock Distribution Tree Operation #2 • The transmitted strobe (and data) signals are generated from the on-chip bus clock. • Typically, the strobe is phase shifted by ½ cycle from the data signal. Some buses do the shifting in the receiver. • Duty cycle variations will cause variation on the phase relationship • The timing path starts at the flip-flop of the transmitting agent and ends at the flip-flop of the receiving agent. • The strobe signal is used as the clock input of the receiver flip-flop. Signal Parameters & Timing Class 3

10. Driver Chip From Core D Q D DELAY n Strobe n n From Core D Q P L Data L Clock Distribution Tree Data Receiver Chip To Core Q D Q D System n Clock Strobe P L L Clock Distribution Tree Operation #2 • Typically, there is one strobe signal (or pair of signals) per two bytes of data signals. • Varies by design • Signal relationships at the transmitter are shown below. Signal Parameters & Timing Class 3

11. @ RECEIVER Truman Thmar Tsu Th STROBE/STROBE Thskew Tsuskew Tvb Tva @ DRIVER DATA t Source Synchronous Operation Tsuskew: flight time skew for setup Tsumar: setup margin Tvb: min driver phase offset (setup) Thskew: flight time skew for hold Thmar: hold margin Tvb: min driver phase offset (hold) Signal Parameters & Timing Class 3

12. Truman Thmar STROBE/STROBE Tvb Tva @ DRIVER DATA Source Synchronous Equations @ RECEIVER Tsu Th Thskew Tsuskew The sum of the timings at the receiver must equal the timing at the driver: This implies that we must design with minimum driver offsets: Signal Parameters & Timing Class 3

13. Truman Thmar STROBE/STROBE Tvb Tva @ DRIVER DATA Source Synchronous Equations #2 @ RECEIVER Tsu Th Thskew Tsuskew We must also satisfy the following relationship: This determines our maximum transfer rate. Signal Parameters & Timing Class 3

14. Question • Based on what we’ve covered in the previous slides, what are the implications to: • The transmitter design? • The receiver design? • The interconnect design? • Example: • Tsu = 500 ps, Th = 250 ps • The target transfer rate is 500 MT/s. • What are reasonable flight time skew targets? Signal Parameters & Timing Class 3

15. TBCLK DRIVER STB/STB DRIVER DATA RECEIVER STB/STB RECEIVER DATA Setup Timing Diagram & Loop Analysis TBCLK BCLK /4 DCLK Tco(STB) Tco(DATA) Tflight(STB) Tflight(DATA) Tsu Tsumar Signal Parameters & Timing Class 3

16. Setup Analysis • For a “double pumped” bus, the difference between Tco(DATA) and Tco(STB) is typically set to one-half of the cycle time (TDCLK/2 = TBCLK/4) to center the strobe in the data valid window. • Double pumped: source synchronous transfer rate is 2x the central clock rate. • This relationship is typically specified as Tvb (data “valid before” strobe ), which signifies the minimum time for which the data at the transmitter is valid prior to transmission of the strobe. • Mathematically: • Simplify the loop equation: Signal Parameters & Timing Class 3

17. Setup Analysis #2 • Both data & strobe propagate over the interconnect. • Goal: identical flight times. • In reality, there will be some difference in flight times between data and strobe. • trace length, loading, crosstalk, ISI, etc. • Define flight time skew for the setup condition: • Simplify the loop equation: Signal Parameters & Timing Class 3

18. Notes on the Setup Equation • You may see the timing equation written in other forms. • The way we defined Tvb makes it a negative quantity. Others may define it to be positive. • We defined Tsuskew to be a positive quantity. Signal Parameters & Timing Class 3

19. TBCLK BCLK TBCLK/4 DCLK Tco(STB) Tco(DATA) DRIVER STB/STB Tflight(STB) DRIVER DATA Th RECEIVER STB/STB Tflight(DATA) Thmar RECEIVER DATA Hold Timing Diagram & Loop Analysis Signal Parameters & Timing Class 3

20. Hold Analysis • Just as for the setup case, we need to specify the minimum phase relationship between data and strobe: • In addition, define the flight time skew for the hold case: • In addition, define the flight time skew for the hold case: • Note that the Thskew is defined such that it is a negative quantity, while Tva is defined to be positive. Signal Parameters & Timing Class 3

21. -T T vb,min va,min STB/STB DATA T cycle,min Maximum Transfer Rate • The maximum transfer rate can be determined using the definitions for Tva and Tvb. • We can calculate the limit of TBCLK (for a double pumped bus) by adding the two equations above. Signal Parameters & Timing Class 3

22. Higher Transfer Rates (e.g. “Quad Pumped”) • The setup and hold equations remain the same. • What changes are the Tva and Tvb definitions: Signal Parameters & Timing Class 3

23. Part C: Edge Considerations and Real Specs Signal Parameters & Timing Class 3

24. Review Edge Triggered Clocking Data in (d) Data out (Q) D-Latch clock (clk) Data in (d) Clock to out time or data valid time clock (clk) Holdtime Data out (Q) Set up time Signal Parameters & Timing Class 3

25. Finer look at the latch Data in • First stage is a buffer • Converts to internal digital levels • Its convenient to think of buffer as differential comparator Internal output Threshold Buffer delay time Threshold Data in Internal output Signal Parameters & Timing Class 3

26. The transfer function of the input buffer is linear for only for a very small region on a input signals edge. We want it to work in the saturation region above and below threshold. This is so the output is either is high or low and converted to the internal voltage representation of high or low. I.e. binary The assumption is that the signal edge is sufficiently fast enough to guarantee predictable switching of high to low and visa-versa. Switching Threshold Linear Region Saturated Region SI engineers often measure slew rate as a reported budget parameter Signal Parameters & Timing Class 3

27. Vil is the voltage required to switch the output of the input buffer to a low state. Vih is the voltage required to switch the output of the input buffer to a high state. Vil and Vih Data in Vih Vil Signal Parameters & Timing Class 3

28. Relation to timing Transmitter out out into reference load • Transmitter output times are measured at a threshold level. • This is how the Tco’s are measured. • Max and min values reported in budgets are normally • The maximum of all the design configuration and process variations max values • The minimum of all the design configurations and process variations min values. Output Reference Threshold Input to Receiver Min low going edge Flight time Vih Max high going edge Flight time Min high going edge Flight time Max low going edge Flight time Vil Signal Parameters & Timing Class 3

29. Assignment: Determine Tva and Tvb • Give UI (unit interval = 10 ns) • Meaning 20ns period and 10ns bit time with sufficiently fast rise time • The sources are 1 Volt with source resistance of 50 ohms • Data has 5pF tied to it • Strobe has 10p tied to it. • The threshold voltage VOL and VOH are 0.8 v • What are Tva and Tvb Signal Parameters & Timing Class 3