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Digital System Design

Digital System Design. Intro. VLSI: CMOS inverter. CMOS inverter: black and white representation. A counter layout. Rules for design rule checking: basic rules. Rules for composition. Concept of the State Machine Example : Odd Parity Checker. Next State/Output Functions.

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Digital System Design

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  1. Digital System Design

  2. Intro. VLSI: CMOSinverter

  3. CMOS inverter: black and white representation

  4. A counter layout

  5. Rules for design rule checking:basic rules

  6. Rules for composition

  7. Concept of the State Machine Example: Odd Parity Checker Next State/Output Functions NS = PS xor PI; OUT = PS T FF Implementation D FF Implementation Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0

  8. State Behavior of R-S Latch Truth Table Summary of R-S Latch Behavior

  9. 7474 D Q Clk Positive edge-triggered flip-flop Bubble here for negative edge triggered device Sequential Switching Networks D-FlipFlop Edge triggered device sample inputs on the event edge

  10. Cascaded Flipflops and Setup/Hold/Propagation Delays Shift Register S,R are preset, preclear New value to first stage while second stage obtains current value of first stage Correct Operation, assuming positive edge triggered FF

  11. Design Procedure Excitation Tables: What are the necessary inputs to cause a particular kind of change in state?

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