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GHDL Tutorial. From http://mbmn.net/uer/tutorials/vhdl-with-ghdl/. Makefile. # vhdl files FILES = src /* VHDLEX = . vhd # testbench TESTBENCHPATH = testbench /${TESTBENCH}$(VHDLEX) #GHDL CONFIG GHDL_CMD = ghdl GHDL_FLAGS = -- ieee = synopsys --warn-no-vital-generic

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Ghdl tutorial

GHDL Tutorial

From http://mbmn.net/uer/tutorials/vhdl-with-ghdl/


Makefile
Makefile

# vhdl files

FILES = src/*

VHDLEX = .vhd

# testbench

TESTBENCHPATH = testbench/${TESTBENCH}$(VHDLEX)

#GHDL CONFIG

GHDL_CMD = ghdl

GHDL_FLAGS = --ieee=synopsys --warn-no-vital-generic

SIMDIR = simulation

# Simulation break condition

#GHDL_SIM_OPT = --assert-level=error

GHDL_SIM_OPT = --stop-time=500ns

WAVEFORM_VIEWER = gtkwave

all: compile run view

new :

echo "Setting up project ${PROJECT}"

mkdirsrctestbench simulation

compile :

ifeq ($(strip $(TESTBENCH)),)

@echo "TESTBENCH not set. Use TESTBENCH=value to set it."

@exit 2

endif

mkdir -p simulation

$(GHDL_CMD) -i $(GHDL_FLAGS) --workdir=simulation --work=work $(TESTBENCHPATH) $(FILES)

$(GHDL_CMD) -m $(GHDL_FLAGS) --workdir=simulation --work=work $(TESTBENCH)

@mv $(TESTBENCH) simulation/$(TESTBENCH)

run :

@$(SIMDIR)/$(TESTBENCH) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(TESTBENCH).vcdgz

view :

gunzip --stdout $(SIMDIR)/$(TESTBENCH).vcdgz | $(WAVEFORM_VIEWER) --vcd

clean :

$(GHDL_CMD) --clean --workdir=simulation


Source src and 2 vhd
Source: src/and_2.vhd

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity and_2 is

port ( a, b : in std_logic;

c : out std_logic );

end entity;

architecture behav of and_2 is

begin

c <= a and b;

end behav;


Testbench testbench and 2 tb vhd
Testbench: testbench/and_2_tb.vhd

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity and_2_tb is

end entity;

architecture TB of and_2_tb is

component and_2

port( a, b: in std_logic;

c : out std_logic);

end component;

signal sa, sb, sc: std_logic;

begin

a : and_2 port map(a => sa, b => sb, c => sc);

sa <= '0' after 0 ns, '1' after 30 ns, '0' after 60 ns, '1' after 90 ns;

sb <= '0' after 0 ns, '1' after 15 ns, '0' after 30 ns, '1' after 45 ns, '0' after 60 ns, '1' after 75 ns, '0' after 90 ns;

end TB;


Usage
Usage

  • make TESTBENCH=and_2_tb


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