Pll for ttcex re design
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PLL for TTCex re-design. S. DETRAZ PH-ESE-BE 20/11/2008. Clock/Orbit Fanout board. Reminder: TTC system (1). RF_Rx_D receiver boards (to receive: BC1, BC2, BCRef, Orbt1, Orbt2, BST). RF2TTC board. CTP (Central Trigger Processor)*. Experiment responsibility.

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PLL for TTCex re-design

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Pll for ttcex re design

PLL for TTCex re-design

S. DETRAZ

PH-ESE-BE

20/11/2008

S.DETRAZ PH-ESE


Pll for ttcex re design

Clock/Orbit Fanout board

Reminder: TTC system (1)

RF_Rx_D receiver boards

(to receive: BC1, BC2, BCRef, Orbt1, Orbt2, BST)

RF2TTC board

CTP (Central Trigger Processor)*

Experiment responsibility

S.DETRAZ PH-ESE

*CTP is a denomination used by ATLAS & ALICE, the same functionality is called GT (Global Trigger) for CMS. LHCb has a different concept


Pll for ttcex re design

Reminder: TTC system (2)

ATLAS

CMS

+RF2TTC

S.DETRAZ PH-ESE


Reminder ttc frame encoding

Reminder: TTC frame encoding

A and B channels are time division multiplexed.

Biphase Mark encoding is used at 160MBaud (balanced signal).

Thus we need 160MHz clock to encode the data on the TTCex.

S.DETRAZ PH-ESE


Atlas ttc clock specification

ATLAS TTC clock specification

All clocks on the FEB are derived from a single input 40 MHz clock. The clock used to sample the calorimeter signals must be of excellent quality if the ultimate timing resolution achievable by the LAr calorimeter, of order a few tens of ps, is to be approached. Furthermore, the FEB serial output data link operates at 1.6 Gb/s. Since this high frequency clock must be derived by multiplying the 40 MHz clock, stable operation of the output optical link requires an input clock with very low jitter.

The input 40 MHz clock is recovered on the FEB from the input TTC signal, via the on-board

TTCrx chip. The TTCrx includes an on-chip phase-locked-loop (PLL) circuit with a wide lock

range, but provides a recovered clock with rather large random and TTC data-dependent jitter.

During the first round of prototype FEB production, it was discovered that the jitter levels were

too high to prevent stable operation of the optical link. To solve this problem, the FEB design

was modified to include the QPLL chip. The QPLL is a PLL based on a voltage-controlled

quartz crystal oscillator (with external crystal), developed as a jitter filter for the TTCrx clock and

implemented in the DSM process. The QPLL has a narrow lock range, typically less than 8 kHz,

and should provide an output clock with less than 50 ps jitter peak-to-peak.

S.DETRAZ PH-ESE


Ttcex

TTCex

  • The TTCex input clock comes from various boards (LTP, TTCcf) but was last filtered on the RF2TTC with the help of a QPLL chip.

  • The TTCex input clock can be switch from the real BC to local LHC clock.

  • The RF2TTC provides also programmable delay on the BC.

    The clock has to be cleaned and the frequency has to be multiplied on the

    TTCex → a PLL is needed.

    This PLL will have to comply (at least) with the QPLL frequency range and to

    stand phase jump due to clock switching and delay on the RF2TTC (or other

    upstream boards).

S.DETRAZ PH-ESE


Pll selection

PLL selection

  • As explained on the previous presentation, we found two families of components which could do the “job”:

    • The LMK3000 “clock jitter cleaner” family from National Semiconductor.

    • The Si53xx “any rate clock” family from SiliconLabs.

    • Certainly other components exist on the market but… it is a good start.

      Some of these components need configuration. This implies on board “intelligence” - thus we need a uprocessor or a CPLD and a memory to retain the configuration data.

      Even if it exists tiny ucontroler with onboard memory, this solution requires extra space and extra complexity.

      We chose to avoid component with active configuration. Thus only few parts of the Si53xx family can be considered -> the pin controlled parts. For these components the configuration can be done with resistors.

      Only 2 references from the pin controlled parts provide clock multiplication -> Si5323 and Si5366.

      We have got sample and evaluation boards for Si5323 and LMK3000C… so let’s start with these components.

S.DETRAZ PH-ESE


Silicon labs any rate precision clock

Silicon Labs: Any-Rate Precision Clock

Silicon labs proposes a so called “any-rate precision clock” for jitter attenuation and frequency multiplication.

This component integrates most of the PLL elements (phase comparator, filter, VCXO, dividers…) on one chip.

It uses the patented DSPLL technology.

This component uses a Digital Signal Processor to implement the PLL filter and a very low jitter Digitally Controlled Oscillator.

S.DETRAZ PH-ESE


Si5323 overview

Si5323 Overview

With more configuration: Si5323

  • The device accepts & provides clocks in the SONET& DATACOM frequency ranges. The two input clocks are at the same frequency. The two output clock are at the same frequency.

  • The multiplication ratio between input & output clock is selectable from predefined values.

  • The PLL loop bandwidth is selected from different values (depending on the frequency plan)

  • Output phase adjustment (200ps increment)

  • Automatic selection between 2 input clocks.

  • Hitless switching possible.

  • Loss of signal and loss of lock alarms.

  • PLL Bypass

  • Output driver: various signal formats (CML, LVDS, LVPECL, CMOS)

S.DETRAZ PH-ESE


Ns lmk03000 precision clock conditioner

NS LMK03000 precision clock conditioner

  • Fully integrated very low noise VCO.

  • Clock output frequency range: 1 to 785MHz

  • 8 outputs clock with independent delay and frequencies.

  • Partially integrated loop filter.

  • Programmable delay (150ps steps)

  • Programmable through MicroWire (SPI)

S.DETRAZ PH-ESE


Si5323 pll capture lock range 1

Si5323: PLL capture & lock range (1)

The Si5323 proposes different ranges of input frequency corresponding to the SDH/SONET telecom standard.

The closest SONET frequency for the TTC application is 38.88MHz.

The component configuration/simulator software (DSPLLsim) specifies the following input frequency range: 37.890625MHz to 40.000000MHz.

The TTC (QPLL) frequency range: 40.0823 to 40.0749 MHz is slightly beyond the component specified input frequency range.

We have to check if the actual range is larger than the specified one.

S.DETRAZ PH-ESE


Pll capture lock range 2

PLL capture & lock range (2)

After a frequency scan, we found that the component can capture and keep the lock between 33 & 52MHz.

We checked the jitter attenuation at these 2 extreme frequencies:

Input signal jitter characteristics (52MHz):

C2C -> 360ps pp, 49ps rms

TIE (LBW: 5.2kHz) -> 150ps pp, 21ps rms

PLL output signal jitter characteristics (208MHz):

C2C -> 45ps pp, 5ps rms

TIE (LBW: 20.8kHz) -> 21ps pp, 2.3ps rms

Oscilloscope: 200us/div, 10Gs/s, single shot (416E3 values).

We found close values for 33MHz.

We haven’t checked the other component characteristics at these two extreme frequencies.

S.DETRAZ PH-ESE


Jitter characterization setup 1

Jitter characterization setup (1)

  • Jitter generation:

    We use AGILENT 81133A 3.35GHz pattern generator.

    This generator provides a very low jitter clock (<4ps RMS).

    The output clock has a phase control input. We connected this input to function generator providing a programmable sinusoidal waveform.

We used the +/-250ps delay range.

The sinusoid has +/-250mVpp which should provide around +/-62ps of jitter.

Rk: We are not fully confident in the delay linearity over all the frequency range.

S.DETRAZ PH-ESE


Jitter characterization setup 2

Jitter characterization setup (2)

  • Jitter measurement could be tricky and require to well define the measurement set-up and method.

    We used Lecroy WaveRunner 104xi oscilloscope. It is a 1GHz and 5 to 10Gs oscilloscope providing some mathematic functions to measure signal jitter.

    For all the following TIE jitter measurement we set the lower jitter frequency bandwidth by using the oscilloscope internal PLL:

    We used FC GOLDEN PLL.

    PLL cutoff requency:Input clock: 1kHz.

    Output clock 1.6kHz.

    There are some other parameters limiting the lowest jitter frequency we are able to measure. One, is the timebase used (and the memory depth). Indeed with a 100us/div time base, ideally the lowest frequency we can measure is 1kHz.

    The oscilloscope long-term timebase accuracy is also a limiting factor.

S.DETRAZ PH-ESE


Reference measurement without jitter generation si5323

Reference measurement (without jitter generation)Si5323

  • BW: 7.7kHz

  • BW: 110Hz

S.DETRAZ PH-ESE


Reference measurement without jitter generation lmk3000c

Reference measurement (without jitter generation)LMK3000C

  • BW: 59.1kHz

  • BW: 77Hz

S.DETRAZ PH-ESE


Jitter attenuation

Jitter attenuation

Low frequency jitter (<1MHz) can only be seen on the TIE measurement.

Jitter attenuation = 20 LOG10 (Input clock Jitter / Output clock jitter)\\

For the following graphs, the input & output clock jitters are TIE peak to peak jitters .

S.DETRAZ PH-ESE


Jitter attenuation si5323

Jitter attenuationSi5323

S.DETRAZ PH-ESE


Jitter attenuation lmk3000c

Jitter attenuationLMK3000C

S.DETRAZ PH-ESE


Phase change with delay25

Phase change with delay25

On the RF2TTC a delay25 ASIC component allows us to shift the clock signal by 0.5ns steps.

This phase shift is applied before the QPLL on the RF2TTC clock path. A large phase shift can cause the QPLL to unlock.

The larger absolute phase skew is 12.5ns which correspond to 25 steps of the delay25. But this value causes the QPLL to unlock. The QPLL can take several tens ms to relock.

C2: RF2TTC BC1, C3: RF2TTC BC2, F1: SKEW (C2 & C3)

S.DETRAZ PH-ESE


Phase change with delay251

Phase change with delay25

A 5ns phase shift will keep the clock locked.

C2: RF2TTC BC1, C3: RF2TTC BC2, F1: SKEW (C2 & C3)

We will test the PLL with both cases.

S.DETRAZ PH-ESE


Si5323 phase change with delay25 5ns step

Si5323 - Phase change with delay25: 5ns step

PLL BW: 112Hz

F1: Skew between PLL input clock (BC1) & PLL output clock

F2: Skew between RF2TTC BC1 & BC2

S.DETRAZ PH-ESE


Si5323 phase change with delay25 5ns step1

Si5323 - Phase change with delay25: 5ns step

PLL BW: 452Hz

F1: Skew between PLL input clock (BC1) & PLL output clock

F2: Skew between RF2TTC BC1 & BC2

S.DETRAZ PH-ESE


Si5323 phase change with delay25 5ns step2

Si5323 - Phase change with delay25: 5ns step

PLL BW: 7.7kHz

F1: Skew between PLL input clock (BC1) & PLL output clock

F2: Skew between RF2TTC BC1 & BC2

S.DETRAZ PH-ESE


Si5323 phase change with delay25 12 5ns step

Si5323 - Phase change with delay25: 12.5ns step

PLL BW: 112Hz

F1: Skew between PLL input clock (BC1) & PLL output clock

F2: Skew between RF2TTC BC1 & BC2

S.DETRAZ PH-ESE


Si5323 phase change with delay25 12 5ns step1

Si5323 - Phase change with delay25: 12.5ns step

PLL BW: 452Hz

F1: Skew between PLL input clock (BC1) & PLL output clock

F2: Skew between RF2TTC BC1 & BC2

S.DETRAZ PH-ESE


Si5323 phase change with delay25 12 5ns step2

Si5323 - Phase change with delay25: 12.5ns step

PLL BW: 7.7kHz

F1: Skew between PLL input clock (BC1) & PLL output clock

F2: Skew between RF2TTC BC1 & BC2

S.DETRAZ PH-ESE


Si5323 clock switching on the rf2ttc

Si5323 - Clock switching on the RF2TTC

The clock can be switch from internal to external (or reverse) on the RF2TTC. We have checked that nothing wrong happen for the Si5323 because of this clock change.

C2: Si5323 CKOUT, C3: RF2TTC BC1out, F1: SKEW (C3 & C2)

500us/div, 5Gs/s

F1 y scale: 1ns/div

S.DETRAZ PH-ESE


Lmk3000c phase change with delay25 5ns step

LMK3000C - Phase change with delay25: 5ns step

PLL BW: 59kHz

F1: Skew between PLL input clock (BC1) & PLL output clock

F2: Skew between RF2TTC BC1 & BC2

S.DETRAZ PH-ESE


Lmk3000c phase change with delay25 5ns step1

LMK3000C - Phase change with delay25: 5ns step

PLL BW: 77Hz

F1: Skew between PLL input clock (BC1) & PLL output clock

F2: Skew between RF2TTC BC1 & BC2

S.DETRAZ PH-ESE


Lmk3000c phase change with delay25 12 5ns step

LMK3000C - Phase change with delay25: 12.5ns step

PLL BW: 59kHz

F1: Skew between PLL input clock (BC1) & PLL output clock

F2: Skew between RF2TTC BC1 & BC2

S.DETRAZ PH-ESE


Lmk3000c phase change with delay25 12 5ns step1

LMK3000C - Phase change with delay25: 12.5ns step

PLL BW: 77Hz

F1: Skew between PLL input clock (BC1) & PLL output clock

F2: Skew between RF2TTC BC1 & BC2

S.DETRAZ PH-ESE


Constant delay between input output clock

Constant delay (between input & output clock)

The component has to introduce a constant delay in the clock path.

The component provides a so called “phase build-out” function to avoid phase transient during clock switching. This function has to be disabled to keep a constant phase between input & output clocks.

For a given frequency range (40.09 to 40.06MHz ), the phase is kept constant most of the time:

  • When we plug/unplug the input clock.

  • when we change the input clock phase (delay25) or switch the clock (on the rf2ttc).

    But this phase change in some cases:

    Most of the time switching the component power supply on/off/on do not change the delay but it appears that in some cases the delay jump about 390ps (2x195ps) and in a very rare cases 1969ps (10x195ps).

    The component provides output phase adjustment in order of 200ps steps (its internal oscillator period) via 2 pins: DEC & INC. If these pins are tied to Vdd, the phase should remains the same.

    We have to investigate more this problem. It could be due to the voltage rise time.

S.DETRAZ PH-ESE


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