Rich Katz, Grunt Engineer NASA Office of Logic Design

1. RTAX-SThings for Design Engineers to Consider Rich Katz, Grunt Engineer NASA Office of Logic Design

2. Objective • Understand subtle specifications and characteristics to prevent misapplication of the device. Reference and additional information “RTAX-S and AX Application Notes” http://klabs.org/richcontent/fpga_content/DesignNotes/rtax-s_ax

3. RTAX-S General Purpose I/O’sAre Not SEE Hardened. • Use clock inputs for clock and other edge sensitive inputs such as reset signals. “The RTAX-S single-ended, differential, and voltage-referenced I/O structures are not radiation-tolerant and are subject to SEE.” Source: “RTAX-S Radiation-Tolerant Features and Mitigation Techniques,” January 2005, Actel Corporation.

4. Ground The TRST* Pin • Ground this pin • Verify it is grounded with an ohm meter • System functional testing can not determine state of this pin • Do not ground it through a resistor • TRST* has an internal pull up (unless disconnected which is not recommended) • Boards should be manufactured with termination installed • Then you can’t forget to install it at the end of the test program References: NASA Advisory NA-GSFC-2004-04 – “TRST* and the IEEE JTAG 1149.1 Interface” http://www.klabs.org/richcontent/maplug/notices/na-gsfc-2004-04.pdf "Use of SX Series Devices and IEEE 1149.1 JTAG Circuitry“ http://www.klabs.org/richcontent/fpga_content/SX_Series/JTAG_SX_WhitePaper.PDF

5. Ground The VPUMP Pin • Ground this pin too. VPUMP Supply Voltage (External Pump) In low-power mode, VPUMP will be used to access an external charge pump (if the user desires to bypass the internal charge pump to further reduce power). The device starts using the external charge pump when the voltage level on VPUMP reaches 3.3V. When VPUMP = 3.3V, it shuts off the internal charge pump. In normal device operation, when using the internal charge pump, VPUMP should be tied to GND.

6. PLL Terminations • RTAX-S: PLL deleted from silicon • RTAX-S pins are “no connects” • PLL supply voltage pins (VCCPLX and VCOMPLX) can be driven to any voltage or left floating. • AX: Often used for prototyping • VCCPLX: connect directly to 1.5V • VCOMPLX: do not connect • R’s and C’s: do not install (used for filtering) Standard AX PLL Configuration Reference “The PLL and Prototyping RTAX-S FPGAs” http://klabs.org/richcontent/fpga_content/DesignNotes/rtax-s_ax/pll_proto/

7. Part Densities (1) • Part numbers do not directly indicate the amount of logic resources Table I.  Architectural logic resources of RTSX-SU and RTAX-S Note that there are some capacity improvements in the RTAX-S FPGAs that are not accounted for in the table. This extra capacity comes from RTAX-S architectural additions relative to the RTSX-SU: *Flip-flops in the I/O Cells (input, output, and enable registers) *Carry chain logic *Buffer modules in each super cluster and I/O cluster Additionally note that each RAM block in RTAX-S consists of 4,608 bits. There is no block RAM present in RTSX-SU.

8. Part Densities (2) • Part numbers do not directly indicate the amount of logic resources Table II.  Architectural logic resources normalized to the RTSX32SU Note that there are some capacity improvements in the RTAX-S FPGAs that are not accounted for in the table. This extra capacity comes from RTAX-S architectural additions relative to the RTSX-SU: *Flip-flops in the I/O Cells (input, output, and enable registers) *Carry chain logic *Buffer modules in each super cluster and I/O cluster Additionally note that each RAM block in RTAX-S consists of 4,608 bits. There is no block RAM present in RTSX-SU.

9. Action Probe (1) • RTAX-S Probe Points • Increased to 4 per device • Limit: Only two probe points per tile RTAX-S architecture consists of tiles

10. Action Probe (2) • ACTION PROBE LIMITATIONS • The Action Probe has some limitations on what can be probed in the RTAX-S architecture, as listed below.  The following can not be probed: • Input registers • Output registers • HCLK • CLKBUF • Restriction 4, not being able to probe CLKBUF's, suggests that the designer should use an INBUF + CLKINT pair to source a signal onto the routed array clock distribution network.  However, since only the clock inputs are SET hardened, it is not clear that using an INBUF instead of a CLKBUF in the I/O Cell will retain the SET hardness.  This open item has been sent to Actel for resolution.  • Another approach for probing the routed array clock is to bring the clock signal on-chip using the SET hardened CLKBUF and then use a C-Cell to provide the path to the Action Probe circuits.  Ensure that the buffering logic element is not optimized out of the netlist. Preliminary

11. Action Probe (3) TERMINATE SPECIAL PINS PROPERLY The following are the special pins and must be properly terminated for reliable operation: • PRA/B/C/D (Probes A, B, C, and D): Output.  Do not connect. • TCK (Test Clock): No internal resistor.  Terminate to either VCCDA or ground.  Do not leave floating. • TDI (Test Data Input): Internal pullup resistor.  Either do not connect or terminate to VCCDA. • TDO (Test Data Output):  Output.  Do not connect. • TMS (Test Mode Select): Internal pullup resistor.  Either do not connect or terminate to VCCDA. • TRST (Boundary Scan Reset Pin): This pin is more complex as in RTAX-S the internal pull-up resistor, required by the IEEE JTAG standard, is optional.  It is recommended at this time, for consistency, to enable the pull-up resistor and treat this pin as in previous generation of Actel components and other IEEE JTAG compatible devices.  As such, the pin should be terminated to ground via 0 ohms, which is critical for flight safety.  This 0 ohm termination obviously needs to be removed for debugging.

12. Action Probe (4) Silicon Explorer terminations for RT54SX-SU.  RTAX-S terminations are similar.

13. Action Probe (5) On-board resistors are used to provide proper signal integrity for Silicon Explorer and RTAX-S FPGA communications. See figure on previous chart for proper terminations of the TCK and TRST* pins.

14. LVDS Input/Outputs Concentrating on LVDS since that is a popular electrical standard for aerospace systems and there are implications for RTAX-S applications.

15. LVDS Input/Outputs (1) But RTAX-S does not drive LVDS …

16. LVDS Input/Outputs (2) … three external resistors required. PECL interface uses the same circuit topology with different resistor values.

17. LVDS Input/Outputs (3) RTAX-S architecture has 8 “I/O Banks”

18. LVDS Input/Outputs (4) • I/O standards may not be arbitrarily mixed within a bank • Each bank has it’s own VCCI and VREF which determine what standards are supported • Example: LVDS and +3.3V I/O may not reside in the same I/O bank

19. RTAX-S FPGA 100 +5V Compatibility • RT54SX • Drive: Capability to drive to 3.3V • Input: +5V input tolerant • RT54SX-S and RTSX-SU • Drive: Capability to drive to +5V rail • Input: +5V input tolerant • RTAX-S • Drive: Can only drive to +3.3V • Voltage margin in receiver device • Delta ICC in receiver device • Input: Not +5V input tolerant • Ugly “kludge” with PCI inputs

20. Memory SEU Hardening • RTAX-S SRAM not hardened by design (data from AX) • Two methods of hardening • Use EDAC macro • Use SEU-hardened R-Cells, exploiting the high-density of the device From “Single Event Upset and Hardening in 0.15µm Antifuse-Based FPGA,” J.J. Wang, W. Wong, S. Wolday, B. Cronquist, J. McCollum, R. Katz, and I. Kleyner, 2003 IEEE NSREC

21. Kill It With Margin • Design conservatively. Or else.