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CMS Tracker FED - Front End FPGA DDR-DCI-I/O

CMS Tracker FED - Front End FPGA DDR-DCI-I/O. Clock 40. 3. Clock40. Reset. adc enables. 18. Opto Rx. 6. Frame_Sync_out. Frame_Sync_In. 8. 2 x Temp Sense. Readout_Sync_out. 4. DAC Serial. Readout_Sync_In. Monitor_Sync_out. delay_ser_out. Monitor_Sync_In. 3.

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CMS Tracker FED - Front End FPGA DDR-DCI-I/O

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  1. CMS Tracker FED - Front End FPGADDR-DCI-I/O Clock 40 3 Clock40 Reset adc enables 18 Opto Rx 6 Frame_Sync_out Frame_Sync_In 8 2 x Temp Sense Readout_Sync_out 4 DAC Serial Readout_Sync_In Monitor_Sync_out delay_ser_out Monitor_Sync_In 3 FE - BE I/O = 16 signals Front End FPGA delay_ser_in 3 Config_in busy 3 Config_out ADC_Data_stream_0 5 8 Data_stream ADC_Data_stream_11 5 Full Flags 3 Design I/O Total = 128 Configuration Bank DCI Resistors VBatt Power down JTAG Bank Voltages XC2V1000FG456 - 324 I/O Temp Sense Core Voltage XC2V1500FG676 - 396 I/O

  2. CMS Tracker FED - Front End FPGA Floorplan Die Package Channel 0 FE-BE I/O ADC_Data Control Channel 11 Delay - Opto - ADC Same frame 456 & 676 ? XC2V1000FG456 - 324 I/O Clocks? XC2V1500FG676 - 396 I/O XC2V2000FG676 - 456 I/O XC2V3000FG676 - 484 I/O

  3. Front End Module Circuit12 Channel +/-3.3V 3V VD/3 3.3V 1.5V 1 3.3V 3.3V 22R 1 1 1 DCM 5 10 CLOCK CLK40 100R 3 DC CNTRL RESET 2 Signal Thermal 2 3 Wired or 4 FRS_OUT FRS_IN ROS_OUT 3 5 2 ROS_IN MO_OUT MO_IN 6 SL_OUT SL_IN 8 PD Array Detector 4 DATA OUT 7 Full 8 Partially Full 5 9 3 JTAG 10 DATA 6 11 ‘I2C’ >70° ~70° 12 6 Opto Rx EL2140 AD9218 XC2V40 XC2V1500-3000 LM82

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