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POCPA3 – DESY, May 21-23, 2012. Elettra digital control PS. Bipolar digital control 30 A – 20 V PS Denis Molaro. Content. [email protected] low current PS requirements Why digital? Resolution & Limit cycles DPWM Resolution H-Bridge Toggle Technique ADC Synchronization

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elettra digital control ps

POCPA3 – DESY, May 21-23, 2012

Elettra digitalcontrol PS

Bipolar digital control 30 A – 20 V PS

Denis Molaro

content
Content
  • [email protected] low current PS requirements
  • Why digital?
  • Resolution & Limit cycles
  • DPWM Resolution
  • H-Bridge Toggle Technique
  • ADC Synchronization
  • [email protected] 20 A and 5 A PS
  • INFN Frascati, SPARC PS
  • Conclusion & Consideration

POCPA3 – DESY, 21-23/05/2012

fermi@elettra s ps requirements
[email protected]’s PS requirements
  • Four-quadrant: ±5 A, ±10 V and ±20 A, ±20 V
  • Max Ripple: 30 ppm/FS
  • Long term stability (8h): ±50 ppm/FS
  • Standard Ethernet interface
  • Output current resolution: 16 bit
  • Current set point update rate: 50 Hz (for feedback)
  • Load range: 0.5 – 2 Ω and 0.5 – 400 mH
  • Number of channels: more than 300

POCPA3 – DESY, 21-23/05/2012

why digital
Why digital?
  • Easy of PID modification (wide load range for the same current range)
  • Step response optimization for all PS-magnet combination.
  • Galvanic isolation between current sensor and control electronics

POCPA3 – DESY, 21-23/05/2012

resolution limit cycles
Resolution & Limit Cycles
  • Digital controls are affected by limit cycles

POCPA3 – DESY, 21-23/05/2012

resolution limit cycles1
Resolution & Limit Cycles
  • Three conditions are required to avoid Limit Cycles[1]
  • Output min step < reading min step
    • (i.e. output resolution > reading resolution)
  • 0 < Integral Gain (Ki) < 1
  • Loop stability (with ADC gain)

Hardware

PID parameters

[1] A.V.Peterchev, S.R. Sanders: Quantization resolution and limit cycling in digitally controlled PWM converters IEEE Transaction on Power Electronics, Volume 18, Issue 1, Part 2, Jan. 2003, pp. 301-308

POCPA3 – DESY, 21-23/05/2012

resolution limit cycles2
Resolution & Limit Cycles
  • Whenoutput min step > reading min step →

Limit cycles

POCPA3 – DESY, 21-23/05/2012

resolution limit cycles3
Resolution & Limit Cycles

Whenoutput min step < reading min step →

Stady state stable

POCPA3 – DESY, 21-23/05/2012

resolution limit cycles4
Resolution & Limit Cycles
  • Output min step (H-Bridge):
  • Reading min step:
  • Example (±5A PS):
  • VDC-Link = 12 V
  • IoutRANGE = 10 A
  • ADC-RES = 16 bit

POCPA3 – DESY, 21-23/05/2012

resolution limit cycles5
Resolution & Limit Cycles

Limit cycle condition for VDC-Link= 12 V, IoutRANGE = 10 A and ADC-RES = 16 bit

IoutMIN-STEP [µA]

Due to wide range of resistive load a 19 bit of DPWM resolution is required

RLOAD [Ω]

POCPA3 – DESY, 21-23/05/2012

dpwm resolution
DPWM Resolution
  • Delay-line DPWM has been used (TMS320F2808)
  • Using 4 PWM cycles of dithering
  • 17.8 bit resolution has been achieved

POCPA3 – DESY, 21-23/05/2012

h bridge toggle technique
H-Bridge Toggle Technique
  • A further bit of resolution has been added by a Toggle Technique (Patent Pending) between the two legs of the H-Bridge.
  • For instance with
  • VDC-Link=12, RLOAD=1 and mLSB=1/217.8

POCPA3 – DESY, 21-23/05/2012

h bridge toggle technique1
H-Bridge Toggle Technique
  • A further bit of resolution has been added by a Toggle Technique (Patent Pending) between the two legs of the H-Bridge.
  • Keeping m1 constant, varying m2 (or vice versa)
  • VDC-Link=12, RLOAD=1 and mLSB=1/217.8

POCPA3 – DESY, 21-23/05/2012

h bridge toggle technique2
H-Bridge Toggle Technique
  • Example of Toggle Technique with 2 bit of dithering.

POCPA3 – DESY, 21-23/05/2012

adc synchronization
ADC Synchronization
  • ∑∆ converter has been used (ADS1252: 24 bit, SPI, SOIC 8 package)
  • Problem: ADC hasn\'t a start of conversion

∑∆ ADC

ADC

MOD.

CLOCK

SPI

DSP DPWM

SPI

H-Bridge

POCPA3 – DESY, 21-23/05/2012

fermi@elettra 5a and 20a ps
[email protected] 5A and 20A PS

POCPA3 – DESY, 21-23/05/2012

infn frascati sparc 30a ps
INFN Frascati - SPARC 30A PS

External 24V 3kW Bulk

Magnet/Load

AC mains

Magnet

Interlock

Ethernet

POCPA3 – DESY, 21-23/05/2012

infn frascati sparc 30a ps1
INFN Frascati - SPARC 30A PS

POCPA3 – DESY, 21-23/05/2012

infn frascati sparc 30a ps2
INFN Frascati - SPARC 30A PS

POCPA3 – DESY, 21-23/05/2012

conclusion consideration
Conclusion & Consideration
  • Digital control is very useful for standardize different range of PS
  • Simplifies the additions of extra features (communication, waveforms...)

BUT

  • Requires digital hardware and software experts for development and modifications
  • Introduces electronic components not easy to repair-replace (FPGA)

SO

  • Could we roll back to the old and simple POWER SUPPLY and not waveform generator with OLED display, please?

POCPA3 – DESY, 21-23/05/2012

that s all folks
That’s all Folks!

Thank You

POCPA3 – DESY, 21-23/05/2012

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