半导体集成电路

半导体 集成电路学校：西安理工大学院系：自动化学院电子工程系专业：电子、微电时间：秋季学期

上节课内容要点 • 双极集成电路的基本工艺 • 双极集成电路中元件结构

C S E B 双极集成电路的基本工艺 n+ n+ p P+ P+ n-epi n+-BL P-Si

C S E B p tepi-ox P+ n+ P+ n+ Tepi xmc Tepi n-epi xjc n+-BL P-Si P-Si TBL-up 双极集成电路中元件结构 A A’ 四层三结结构的双极晶体管

相关知识点 隐埋层的作用、电隔离的概念、寄生晶体管

本节课内容 • MOS集成电路的工艺 • P阱CMOS工艺 • N阱CMOS工艺 • 双阱CMOS工艺 • BiCMOS集成电路的工艺

源极(S) 栅极(G) 漏极(D) MOSFET的基本结构 N沟MOS晶体管的基本结构栅极（金属）绝缘层（SiO2）源极漏极 n+ n+ 半导体基板 P型硅基板 MOS晶体管实质上是一种使电流时而流过，时而切断的开关 MOS晶体管的动作

MOS晶体管的立体结构 metal connection to gate polysilicon gate doped silicon top nitride metal connection to drain metal connection to source field oxide gate oxide oxide source drain silicon substrate gate oxide

在硅衬底上制作MOS晶体管 silicon substrate

field oxide oxide silicon substrate

photoresist oxide silicon substrate

Ultraviolet Light Chrome plated glass mask Shadow on photoresist Exposed area of photoresist photoresist oxide silicon substrate

感光区域 非感光区域 photoresist oxide silicon substrate

photoresist photoresist oxide silicon substrate 显影 Shadow on photoresist

photoresist oxide oxide silicon substrate silicon substrate 腐蚀

去胶 field oxide oxide oxide silicon substrate silicon substrate

thin oxide layer gate oxide oxide oxide silicon substrate

gate oxide oxide oxide silicon substrate polysilicon

oxide oxide silicon substrate ultra-thin gate oxide polysilicon gate gate gate

ion beam implanted ions in active region of transistors gate gate oxide oxide silicon substrate Scanning direction of ion beam photoresist Implanted ions in photoresist to be removed during resist strip. drain source

gate gate oxide oxide drain source silicon substrate doped silicon

自对准工艺 • 在有源区上覆盖一层薄氧化层 • 淀积多晶硅，用多晶硅栅极版图刻蚀多晶硅 • 以多晶硅栅极图形为掩膜板，刻蚀氧化膜 • 离子注入

gate drain source silicon substrate

contact holes gate drain source silicon substrate

metal connection to gate polysilicon gate doped silicon top nitride metal connection to drain metal connection to source field oxide gate oxide oxide drain source silicon substrate gate oxide 完整的简单MOS晶体管结构

CMOSFET gate gate oxide oxide oxide p+ p+ n+ n+ P型 si sub

VOUT VIN VDD VSS P+ N+ P+ N+ P+ N+ P- 主要的CMOS工艺 P阱工艺双阱工艺 N阱工艺 VOUT VOUT VIN VIN VDD VDD VSS VSS P+ P+ N+ P+ N+ N+ P+ N+ P+ P+ N+ N+ N- P- N- I-Si N-Si P-Si N+-Si

P-well P-well N+ P+ N+ P+ N+ P+ P N-Si • 掩膜1： P阱光刻

具体步骤如下： 1．生长二氧化硅（湿法氧化）： Si(固体)+ 2H2O  SiO2（固体）+2H2

氧化

2．P阱光刻： 涂胶腌膜对准光源曝光显影

P-well 3．P阱掺杂：刻蚀（等离子体刻蚀）去胶 P+ 硼掺杂（离子注入）去除氧化膜

离子源 离子束高压电源电流积分器

P+ P+ N+ N+ P-well N-Si 有源区：nMOS、PMOS 晶体管形成的区域 • 掩膜2：光刻有源区 SiO2隔离岛 P-well P-well • 淀积氮化硅 • 光刻有源区 • 场区氧化 • 去除有源区氮化硅及二氧化硅

有源区 deposited nitride layer 有源区光刻板 N型p型MOS制作区域 (漏-栅-源)

氮化膜生长 对版曝光 P-well P-well P-well P-well 1. 淀积氮化硅：氧化膜生长（湿法氧化） 2. 光刻有源区：有源区光刻板涂胶

显影 P-well P-well P-well P-well 去除氮化硅薄膜及有源区SiO2 氮化硅刻蚀去胶 3. 场区氧化：场区氧化（湿法氧化）

P-well P+ P+ N+ N+ P-well N-Si • 掩膜3：光刻多晶硅多晶硅栅极 P-well 栅极氧化膜去除氮化硅薄膜及有源区SiO2 • 生长栅极氧化膜 • 淀积多晶硅 • 光刻多晶硅

P-well P-well P-well 淀积多晶硅生长栅极氧化膜多晶硅光刻板 P-well 多晶硅刻蚀涂胶光刻

P+ P+ P-well 掩膜4：P+区光刻 P-well 1、P+区光刻 2、离子注入B+，栅区有多晶硅做掩蔽，称为硅栅自对准工艺。 3、去胶 P+ P+ N+ N+ P-well N-Si

P+ P+ P-well P-well P+ 硼离子注入去胶

掩膜5：N+区光刻 P-well N+ N+ P+ P+ P-well 1、N+区光刻 2、离子注入P+，栅区有多晶硅做掩蔽，称为硅栅自对准工艺。 3、去胶 P+ P+ N+ N+ P-well N-Si

N+ P+ P+ P-well 磷离子注入 N+ N+ P+ P+ P-well 去胶

N+ N+ P+ P+ P-well 磷硅玻璃（PSG) 掩膜6：光刻接触孔 P-well 1、淀积PSG. 2、光刻接触孔 3、刻蚀接触孔 P+ P+ N+ N+ P-well N-Si

N+ N+ N+ N+ N+ N+ N+ N+ P+ P+ P+ P+ P+ P+ P+ P+ P-well P-well P-well P-well 刻蚀接触孔掩膜6：光刻接触孔淀积PSG 光刻接触孔去胶

半导体 集成电路