Programmability Issues

1. Programmability Issues Module 4

2. Points to be covered • Types and levels of parallelism • Operating systems for parallel processing, Models of parallel operating systems-Master-slave configuration, Separate supervisor configuration, Floating supervisor control(book3 3.3) • Data and Resource Dependences, Data dependency analysis-Bernstein’s condition • Hardware and Software Parallelism

3. Types and Levels Of Parallelism • Instruction Level Parallelism • Loop-level Parallelism • Procedure-level Parallelism • Subprogram-level Parallelism • Job or Program-Level Parallelism

4. Instruction Level Parallelism • This fine-grained, or smallest granularity level typically involves less than 20 instructions per grain. • The number of candidates for parallel execution varies from 2 to thousands, with about five instructions or statements (on the average) being the average level of parallelism. Advantages: • There are usually many candidates for parallel execution • Compilers can usually do a reasonable job of finding this parallelism

5. Loop-level Parallelism • Typical loop has less than 500 instructions. If a loop operation is independent between iterations, it can be handled by a pipeline, or by a SIMD machine. • Most optimized program construct to execute on a parallel or vector machine. Some loops (e.g. recursive) are difficult to handle. • Loop-level parallelism is still considered fine grain computation.

6. Procedure-level Parallelism • Medium-sized grain; usually less than 2000 instructions. • Detection of parallelism is more difficult than with smaller grains; interprocedural dependence analysis is difficult. • Communication requirement less than instruction level SPMD (single procedure multiple data) is a special case • Multitasking belongs to this level.

7. Subprogram-level Parallelism • Grain typically has thousands of instructions. • Multi programming conducted at this level • No compilers available to exploit medium- or coarse-grain parallelism at present

8. Job Level • Corresponds to execution of essentially independent jobs or programs on a parallel computer. • This is practical for a machine with a small number of powerful processors, but impractical for a machine with a large number of simple processors (since each processor would take too long to process a single job).

9. Data dependence • The ordering relationship between statements is indicated by the data dependence. Five type of data dependence are defined below:- • Flow dependence • Anti dependence • Output dependence • I/O dependence • Unknown dependence

10. Flow Dependence • A statement S2 is flow dependent on S1 if an execution path exists from S1 to S2 and if at least one output (variables assigned) of S1 feeds in as input(operands to be used) to S2 and denoted as-: S1->S2 • Example-: S1:Load R1,A S2:ADD R2,R1

11. Anti Dependence • Statement S2 is antidependent on the statement S1 if S2 follows S1 in the program order and if the output of S2 overlaps the input to S1 and denoted as : S1 S2 Example-: S1:Add R2,R1 S2:Move R1,R3

12. Output dependence Two statements are output dependent if they produce (write) the same output variable. Example-: Load R1,A Move R1,R3

13. I/O • Read and write are I/O statements. I/O dependence occurs not because the same variable is involved but because the same file referenced by both I/O statement. • Example-: S1:Read(4),A(I) S3:Write(4),A(I)

14. Unknown Dependence • The dependence relation between two statements cannot be determined. Example-:Indirect Addressing

15. S1 Load R1, A • S2 Add R2, R1 • S3 Move R1, R3 • S4 Store B, R1 Flow dependency S1to S2 S3 to S4 S2 to S2 Anti-dependency S2to S3 Output dependency S1 toS3

16. Control Dependence • This refers to the situation where the order of the execution of statements cannot be determined before run time. • For example all condition statement,where the flow of statement depends on the output. • Different paths taken after a conditional branch may depend on the data hence we need to eliminate this data dependence among the instructions.

17. This dependence also exists between operations performed in successive iterations of looping procedure. • Control dependence often prohibits parallelism from being exploited.

18. Control-independent example: for (i=0;i<n;i++) { a[i] = c[i]; if (i < 0) a[i] = 1; } • Control-dependent example: for (i=1;i<n;i++) { if (a[i-1] < 0) a[i] = 1; }

19. Control dependence also avoids parallelism to being exploited. • Compilers are used to eliminate this control dependence and exploit the parallelism.

20. Resource dependence • Resource independence is concerned with conflicts in using shared resources, such as registers, integer and floating point ALUs, etc. ALU conflicts are called ALU dependence. • Memory (storage) conflicts are called storage dependence.

21. Bernstein’s Conditions • Bernstein’s conditions are a set of conditions which must exist if two processes can execute in parallel. Notation • Ii is the set of all input variables for a process Pi • . Ii is also called the read set or domain of Pi. • Oi is the set of all output variables for a process Pi .Oi is also called write set.

22. If P1 and P2 can execute in parallel (which is written as P1 || P2) then we should have-:

23. In terms of data dependencies, Bernstein’s conditions imply that two processes can execute in parallel if they are flow-independent, antiindependent, and outputindependent. • The parallelism relation || is commutative (Pi || Pj implies Pj || Pi ), but not transitive (Pi || Pj and Pj || Pk does not imply Pi || Pk )

24. Example of parallelism using Bernstein’s conditions • P1: C = D * E • P2: M = G + C • P3: A = B + C • P4: C = L + M • P5: F = G / E • Assume no pipeline is used, five steps are needed in sequential execution

25. D E D Time P1 * P1 E * G B G E C C P2 G + P2 + P3 + P5 / C P3 B + L M A P4 + P4 M L + C C A F G P5 E / F Example of parallelism using Bernstein’s conditions

26. Example of parallelism using Bernstein’s conditions • Only 5 pairs are possible to execute in parallel P1 || P5, P2 || P3, P2 || P5, P5 || P3, P4 || P5. • Only P2 || P3 || P5 is possible because P2 || P3, P3 || P5 and P2 || P5 are all possible • If two adders are available simultaneously, the parallel execution requires only three steps

27. Hardware and software parallelism • Hardware parallelism is defined by machine architecture. • It can be characterized by the number of instructions that can be issued per machine cycle. If a processor issues k instructions per machine cycle, it is called a k-issue processor. • Conventional processors are one-issue machines.

28. Examples. Intel i960CA is a three-issue processor (arithmetic, memory access, branch). IBM RS -6000 is a four-issue processor (arithmetic, floating-point, memory access, branch)

29. Software Parallelism • Software parallelism is defined by the control and data dependence of programs, and is revealed in the program’s flow graph i.e., it is defined by dependencies with in the code and is a function of algorithm, programming style, and compiler optimization.

30. Software parallelism Totally eight instructions: 4 loads (L), 2 multiplication (X), 1 addition (+) and 1 subtraction (-) Theoretically, the computation will be accomplished in 3 cycles (steps) Step 1 L L L L X X Step 2 + - Step 3 A B Hardware vs. Software parallelism

31. Hardware parallelism (Example 1) By a 2-issue processor which can execute one memory access and one arithmetic operation simultaneously The computation needs 7 cycles (steps) Mismatch between HW and SW parallelism Step 1 L L Step 2 Step 3 X\X L L Step 4 Step 5 X Step 6 + A Step 7 - B Hardware vs. Software parallelism

32. Hardware parallelism (example 2) Using a dual-processor system, each processor is single-issue 6 cycles are needed to execute the 12 instructions, where 2 store operations and 2 load operations are inserted for inter-processor communication through the shared memory Step 1 L L Step 2 L L Step 3 X X Step 4 S S Step 5 L L Step 6 + - A B S statements: added instructions for inter-processor communication Hardware vs. Software parallelism

33. The Role of Compilers • Compilers used to exploit hardware features to improve performance. • Interaction between compiler and architecture design is a necessity in modern computer development. It is not necessarily the case that more software parallelism will improve performance in conventional scalar processors. • The hardware and compiler should be designed at the same time.

34. Operating System For Parallel Processing • There are basically 3 organizations that have been employed in the design of operating system for multiprocessors. They are :- • 1)Master Slave Configuration • 2)Separate Supervisor Configuration • 3)Floating Supervisor Configuration • This classification applies not only to operating system, but in general, to all the parallel programmming strategies.

35. Master Slave Configuration • In the master slave mode, one processor, called master, maintains the status of all the other processors in the system and distributes the works to all the slave processors. • The operating system runs only on master processor and all other processor are treated as schedulable resources. • Other processors needing executive service must request the master that acknowledges the request and performs the services.

36. This scheme is a simple extension of uniprocessor operating system and is fairly easy to implement. • The scheme, however makes the system extremely susceptible to failures.(What if the master fails?) • Many of the slaves have to wait for master’s work to get over,before they can get their request served.

37. Separate Supervisor System • Here in this approach each processor contains the copy of kernal. • Resource sharing occurs via shared memory blocks. • Each processor services its own needs. • If the processor access the shared kernalcode,then the code must be reentrant.

38. Separate supervisor system is less susceptible to failures. • This scheme however demands excess resources for maintaining copies of tables describing resource allocation etc for each of the processors.

39. Floating Supervisor Control • The supervisor routine floats from one supervisor to another although several of the processor may be executing supervisory service routines simultaneously. • Better Load balancing • Several amount of code sharing. • Generally one sees a combination of above schemes to obtain a useful solution.

40. End Of Module 4