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Logic Synthesis 1

Outline Logic Synthesis Problem Logic Specification Two-Level Logic Optimization Goal Understand logic synthesis problem Understand logic optimization problem. Logic Synthesis 1. Map from logic equations to gate-level combinational logic will consider FSM synthesis later Goals

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Logic Synthesis 1

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  1. Outline Logic Synthesis Problem Logic Specification Two-Level Logic Optimization Goal Understand logic synthesis problem Understand logic optimization problem Logic Synthesis 1

  2. Map from logic equations to gate-level combinational logic will consider FSM synthesis later Goals maximize speed minimize power minimize chip/board area Constraints target technology CAD tool CPU time b b c c d d Logic Synthesis Problem a’bc + abc + d bc + d

  3. Two-level logic equations sum of products “PLA format” “ESPRESSO format” Multiple-level logic equations Berkeley Logic Intermediate Format (BLIF) arbitrary set of equations generated in converting directly from RTL e.g. logic equations for ALU generated from gate-level netlist Logic Specification x = abc’ + def + ghi + jkl + ... y = bc + e’ + ghi + jk + ... .i 3 .o 3 .p 4 10x101 x01100 110110 11x010 .e x = ab’ + b’c + abc’ y = abc’ + ab z = ab’ literal operand x = (a(b+c)d + ef(i+j))(k + l)

  4. Logic equations are flattened to two levels AND-OR, NAND-NAND, NOR-NOR common starting point for most tools eliminates any input bias causes exponential explosion in equation size in worst case does not occur in practice Logic Specification • • • • • • • • •

  5. 1. logic equation simplification reduce literal and operand count less “stuff” to implement generally reduces chip area does not always minimize delay 2. logic synthesis map equations to generic gates AND, OR, NOT 3. gate-level optimization “local” transformations for speed, area, power e.g. AND-NOT => NAND need estimate of technology costs 4. technology mapping map from gates to component library FPGAs, standard cells, TTL, etc. Logic Synthesis Problem

  6. Build map - 2N entries label entries 0 - F = 0 1 - F = 1 X - F = don’t care Find minimumprime cover cover - set of terms whose union is true for all entries that are 1 can also cover all 0 entries instead and complement F prime - terms are simplest (largest cover) they can be AB vs. ABC + ABC’ minimum - fewest terms Karnaugh Maps - Two-Level Minimization F = A’BC’D + A’BCD + ABC’D’ + ABC’D + ABCD + ABCD’ + AB’C’D’ + AB’C’D C 0 0 0 0 0 1 1 0 B 1 1 1 1 A 1 1 0 0 D F = AB + AC’ + BD F’ = A’B’ + B’C + A’D’

  7. Examples C C 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 B B 1 1 1 1 1 1 1 1 A A 1 1 0 0 1 1 0 0 D D F = AC’ + BD F = AC’ + BD + ABCD’ F is not a cover ABCD’ is not prime

  8. Examples C C 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 B B 1 1 1 1 1 1 1 1 A A 1 1 0 0 1 1 X X D D F’ = A’B’ + A’D’ + B’C F = A + BD Solve for complement Use don’t care terms when determining if term is prime

  9. Can Get Into Local Minima C C 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 B B 1 0 0 1 1 0 0 1 A A 0 0 0 0 0 0 0 0 D D C C 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 B B 1 0 0 1 1 0 0 1 A A 0 0 0 0 0 0 0 0 D D

  10. Local Minima C C 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 B B 1 0 0 1 1 0 0 1 A A 0 0 0 0 0 0 0 0 D D C C 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 B B 1 0 0 1 1 0 0 1 A A 0 0 0 0 0 0 0 0 D D

  11. Solution try different cover sequences Minimum cover is NP-complete exponential time in worst case Local Minima C C 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 B B 1 0 0 1 1 0 0 1 A A 0 0 0 0 0 0 0 0 D D F = BD’ + A’D’ + A’B’ F = A’B’ + BD’ Result is not minimal Result is minimal Usually many minima

  12. Exponential space in number of inputs e.g. 100 input function needs 2100 cells very inefficient if number of 1 or 0 cells is small Needs of two-level minimization efficient data structure ideally linear in size of function efficient means of searching for minimal prime cover get close to optimal in reasonable time serve as a building-block for multi-level minimization Problems with Karnaugh Maps

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